H. Ishiuchi

Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

The process integration schemes for CMOS FinFET fabricated on bulk Si substrate are discussed from the viewpoints of device size scalability and short channel effect control. The trimming technique by special oxidation was applied to reduce fin width down to sub-10 nm regime. A novel punch through stopper (PTS) formation process was introduced to the bottom of the channel region to scale the gate length down to 20 nm. The combination of both process technology enables us to fabricate the smallest FinFET on bulk Si substrate reported to date

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

35 nm gate length CMOS devices with oxynitride gate dielectric and Ni SALICIDE have been fabricated to study the feasibility of achieving high performance with gate length scaling. The nitrogen profile in the gate oxynitride was optimized to reduce gate current and to prevent boron penetration in the pFET. The thermal budget in MOL & BEOL processes was reduced to realize shallower junction depth in the S/D extension region and to suppress gate poly-Si depletion. Finally, current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/ = 0.85 V (I/sub off/ = 100 nA//spl mu/m) were achieved, which are the best values in 35 nm gate length CMOS reported to date.

Ultrathin gate oxide CMOS on [111] surface-oriented Si substrate

The properties of ultrathin gate oxides in the direct-tunneling regime and the characteristics of the related CMOS transistors on a [111] surface-oriented Si substrate were investigated and compared with those on a [100] substrate for the first time. It was confirmed that low field mobility of n-MOSFETs on the [111] substrate is smaller than that on the [100] substrate and that of p-MOSFETs on [111] is larger than that on [100] until the direct-tunneling gate oxide regime. It has been found that most of the electrical properties of MOSFETs, with the notable exception of mobility, become almost identical for [100] and [111] substrates when the oxide thickness is reduced to less than 2.0 nm. Some of the properties are quite different between the two substrates for the thicker oxide case. It has been found that the reliability of hot carrier injection and time-dependent dielectric breakdown (TDDB) of the oxides and MOSFETs on the [111] substrate is slightly better than that on the [100] substrate. In addition, the characteristics and reliability of oxides and MOSFETs on a wafer tilted 4/spl deg/ from [100] axis were investigated. It was found that there are few differences in the mobility between [100] and [100] 4/spl deg/ off substrates for both n- and p-MOSFET cases. The reliability of oxides or MOSFETs on the wafer was identical to that on normal [100] substrate. These results suggest that ultrathin gate oxide MOSFETs on Si surfaces with various orientations are likely to have practical applications. This is good news for possible future new structures of MOSFETs such as vertical or three-dimensional (3-D) MOSFETs.

Embedded DRAM technologies

Issues on embedded DRAM technologies including their applications, process options, and tradeoffs are discussed. Real implementations of the embedded DRAM technologies with 0.5 /spl mu/m, 0.35 /spl mu/m, and 0.25 /spl mu/m are also presented. The embedded DRAM technologies will be used to realize high bandwidth and low power operation.

Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond

Integration schemes of bulk FinFET SRAM cell with bulk planar FET peripheral circuit are studied for the first time. Two types of SRAM cells with different beta-ratio were fabricated and investigated in the view of static noise margin (SNM). High SNM of 122 mV is obtained in the cell with 15 nm fin width, 90 nm channel height and 20 nm gate length at Vdd = 0.6 V. This is the smallest gate length FinFET SRAM reported to date. A higher beta ratio (beta> 2.0) in FinFET SRAM cell will be also achieved by tuning the effective channel width of each FinFETs without area penalty by taking advantage of bulk-Si substrate

Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension

We present the FinFET process integration technology including improved sidewall transfer (SWT) process applicable to both fins and gates. Using this process, the uniform electrical characteristics of the ultra-small FinFETs of 15nm gate length and 10 nm fin width have been demonstrated. A new process technique for the selective gate sidewall spacer formation (spacer formation only on the gate sidewall, no spacer on the fin sidewall) is also demonstrated for realizing low-resistance elevated source/drain (S/D) extension

An experimental 4-Mbit CMOS DRAM

A 4-Mb dynamic RAM has been designed and fabricated using 1.0-/spl mu/m twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high /spl alpha/-particle immunity was achieved with this structure. One cell measures 3.0/spl times/5.8 /spl mu/m/SUP 2/ yielding a chip size of 7.84/spl times/17.48 mm/SUP 2/. An on-chip voltage converter circuit was implemented as a mask option to investigate a possible solution to the MOSFET reliability problem caused by hot carriers. An 8-bit parallel test mode was introduced to reduce the RAM test time. Metal mask options provide static-column-mode and fast-age-mode operation. The chip is usable as /spl times/1 or /spl times/4 organizations with a bonding option. Using an external 5-V power supply, the row-address-strobe access time is 80 ns at room temperature. The typical active current is 60 mA at a 220-ns cycle time with a standby current of 0.5 mA.

MOSFET design for forward body biasing scheme

Forward body biasing is a solution for continued scaling of bulk-Si CMOS technology. In this letter, the dependence of 30-nm-gate MOSFET performance on body bias is experimentally evaluated for devices with various channel-doping profiles to provide guidance for channel engineering in a forward body-biasing scheme. Furthermore, simulations of 10-nm-gate CMOS (hp22-nm node) devices are performed to study the optimal channel-doping profile and gate work function engineering for a forward biasing scheme.

Impact of BOX scaling on 30 nm gate length FD SOI MOSFET

This paper presents the first demonstration of ultra-thin BOX FD SOI devices with nominal gate length of 30 nm. The characteristics of FD SOI MOSFETs are investigated in detail as T/sub BOX/ is varied from 5 nm to 145 nm. In addition, optimum design regions of T/sub BOX/ for achieving performance requirements are demonstrated.

A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices

High performance 10 nm gate length CMOSFETs for hp22 nm node LOP is demonstrated for the first time. Key process, such as elevated source/drain extension combined with flash lamp annealing, fully silicided metal gate, novel SiON, and optimization method under high V/sub dd/ condition which taking care of SRAM performance is described. Record high transconductance of 1706 mS/mm and over 400 GHz f/sub i/ is achieved for nMOSFET. Bulk planar MOSFET structure can extend down to hp22 nm node.