Kam-Leung Lee

Self-aligned n-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate

In this letter, we report self-aligned n-channel germanium (Ge) MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate electrode. Excellent off-state current is achieved through the reduction of junction leakage. For the first time, we have demonstrated an n-channel Ge MOSFET with a subthreshold slope of 150 mV/dec and an on-off current ratio of /spl sim/10/sup 4/.

Strained Si CMOS (SS CMOS) technology: opportunities and challenges

Abstract Strain-induced enhancement of current drive is a promising way to extend the advancement of CMOS performance. Fabrication of strained Si MOSFET has been demonstrated with key elements of modern day’s CMOS technology. Significant mobility and current drive enhancements were observed. Recent advancements in the SS devices are summarized, and the challenges in device physics/design issues as well as in materials/process integration are highlighted.

High-

Schottky source/drain (S/D) MOSFETs hold the promise for low series resistance and extremely abrupt junctions, providing a path for device scaling in conjunction with a low Schottky barrier height (SBH). A S/D junction SBH approaching zero is also needed to achieve a competitive current drive. In this letter, we demonstrate a CMOS process flow that accomplishes a reduction of the S/D SBH for nFET and pFET simultaneously using implants into a common NiPt silicide, followed by a low-temperature anneal (500°C-600°C). These devices have high-κ/metal gate and fully depleted extremely thin SOI with sub-30-nm gate length.

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ZEP‐520 and KRS resist systems have been evaluated as candidates for use in low voltage electron beam lithography. ZEP‐520 is a conventional chain scission resist which has a positive tone for over two orders of magnitude in exposure dose. KRS is a chemically amplified resist which can be easily tone reversed with a sensitivity ∼8 μC/cm2 at 1 keV. Both resist systems are shown to have sensitivities ∼1 μC/cm2 for positive tone area exposures to 1 keV electrons. A decrease in contrast in 50 nm thick resist layers is seen when exposure voltage is lowered from 2 to 1 keV, indicating nonuniform energy deposition over the resist thickness. High resolution single pass lines have been transferred into both Si and SiO2 substrates at both low and high voltages in each resist system without using multilayer resist masks. The ZEP‐520 and KRS resists are shown to have resolutions of 50 and 60 nm, respectively, at 1 kV, within a factor of 2 of their high voltage resolutions under identical development conditions. A cusp shaped etch profile in Si allows high aspect ratio 20 nm wide trenches to be fabricated using these resists on bulk Si. Low voltage exposures have been used to pattern gratings with periods as small as 75 and 100 nm in ZEP‐520 and KRS, respectively. Low voltage exposures on SiO2 show no indications of pattern distortion due to charging or proximity effects.

/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length

Onium salts and amine triflate salts decompose upon exposure to radiation or thermal treatment respectively to generate protonic acids. These salts can be blended with polyaniline and upon decomposition the resulting acids act as insitu dopants for the polymer. These novel doping techniques eliminate the need for external dopant solutions and thereby simplify the processing of conducting polyaniline.

High resolution electron beam lithography using ZEP‐520 and KRS resists at low voltage

Electrically conducting polyaniline is found to be suitable for several lithographic applications. Because the polyaniline is not significantly soluble in the conducting state, the material has generally been processed by first applying the soluble, nonconducting version of the material, and in a second step externally doping the polymer film with aqueous acids. We have eliminated the need for this type of external doping by developing methods of inducing the doping in a dry fashion in situ in the polymer. This is accomplished by incorporating onium salts or amine triflate salts in the polyaniline which decompose upon radiation or thermal treatment, respectively, to generate the active dopant species, i.e., protonic acids. The use of these in situ dopants simplifies the processing of the conducting polyaniline and makes the material more convenient for lithographic applications. With the use of onium salts, the polyaniline is made into a high resolution negative conducting resist. 0.25 μm conducting lines...

Polyanilines: In Situ Radiation and Thermal Induced Doping

The impact of diffusionless anneal using dynamic surface anneal (DSA) on the electrical properties of p-type metal-oxide-semiconductor devices with high-k gate dielectrics and metal gate was investigated by monitoring flatband voltage (VFB) and equivalent oxide thickness (EOT) change. Compared to rapid thermal anneal, DSA induces a positive VFB shift without EOT degradation. This finding is attributed to suppression of positively charged oxygen vacancies [Vo++] generation in high-k dielectrics due to the shorter thermal budget. Processing parameters including high-k dielectrics, TiN metal gate thickness, and Si cap deposition temperature significantly affect thermally induced-oxygen vacancies, leading to different VFB behaviors.

Lithographic applications of conducting polymers

FinFETs with strained-SiGe channel have recently drawn significant attention due to their built in uniaxial strain, higher mobility and better reliability over conventional Si FETs. Research on pure Ge has been the major focus of many institutes over the past few years. However, with high-Ge-content (HGC) SiGe one can benefit from competitive or better performance over pure Ge and overcome the thermal budget constraints required for Ge. In this paper, we briefly review our latest advancements in high-Ge-content strained-SiGe FinFETs featuring gate first and Replacement HK/MG (RMG) flows with record mobility and short-channel performance to extend the roadmap for advanced FinFET and FDSOI generations.

Impact of diffusionless anneal using dynamic surface anneal on the electrical properties of a high-k/metal gate stack in metal-oxide-semiconductor devices

We demonstrate high-performance (HP) High-Ge-Content (HGC) SiGe pMOS FinFETs with scaled EOT and improved junction. For the first time, SiGe FinFET EOT scaling down to ~7Å has been achieved. In addition, improved junction and series resistance has been demonstrated for HGC SiGe, by a proper choice of spacer thickness and interface-layer as well as hot ion-implant (I/I), resulting in significant R_on reduction down to 250 and 200Ω.μm, respectively. We report the highest “SiGe extrinsic g_m” reported to date with g_{m, LIN}=0.5mS/μm and g_{m, SAT}=2.7/2.5mS/μm at V_DD=1.0/0.5V, the highest HGC SiGe I_on=0.45mA/μm at fixed HP I_off =100nA/μm at V_DD=0.5V and the highest pMOS FinFET performance reported to date at sub-35nm L_G.