Kazuo Kawamura

Si Quantum Dot Formation with Low-Pressure Chemical Vapor Deposition

We report a simple technique for fabricating a layer of isolated Si quantum dots. The procedure uses conventional low-pressure chemical vapor deposition (LPCVD) for an extremely short deposition time in the early stage of poly-Si film growth. The layer resulting from a deposition time of 60 s has isolated Si nanocrystals 5–20 nm in diameter and 2–10 nm in height. Optical absorption measurement shows that the Si-nanocrystal spectrum changes drastically and the onset of absorption shifts to higher energies compared to that of bulk Si. This shift can be explained by the energy gap widening caused by quantum size effects. Special attention is paid to the Brownian migration of Si nanocrystals for fabricating Si quantum dots.

Microstructure and optical absorption properties of Si nanocrystals fabricated with low‐pressure chemical‐vapor deposition

We report a simple technique for fabricating a layer of isolated Si quantum dots on SiO2 glass substrates. This technique uses conventional low‐pressure chemical‐vapor deposition for an extremely short deposition time in the early stage of poly‐Si film growth. The layer after a deposition time of 60 s has isolated Si nanocrystals 5–20 nm in diameter and 2–10 nm in height. The measurements of optical absorption coefficient α show that the absorption edge for Si nanocrystals shifts to higher energies compared to that of bulk Si, indicating a widening of the energy gap caused by quantum size effects. The linear relationship (αhν)1/2 against hν suggests that the Si nanocrystal, whose diameter is as small as 10 nm, basically maintains the properties of an indirect band‐gap semiconductor. Special attention must be paid to the Brownian migration of Si nanocrystals for fabricating Si quantum dots.

Compact model for amorphous layer thickness formed by ion implantation over wide ion implantation conditions

In this paper, a through dose parameter /spl Phi//sub a/c/, which is defined by the dose of ions passing through the amorphous/crystal (a/c) interface, is proposed, and the use of /spl Phi//sub a/c/ combined with parameters for ion-implantation profiles to model the thickness of the amorphous layer d/sub a/ is demonstrated. It is shown that /spl Phi//sub a/c/ is independent of ion-implantation conditions but depends on the impurities. /spl Phi//sub a/c/ for Ge, Si, As, P, B, In, and Sb is evaluated. Consequently, d/sub a/ over a wide range of ion-implantation conditions for various ions was predicted.

Resistivity of Heavily Doped Polycrystalline Silicon Subjected to Furnace Annealing

We investigated the dependence of the resistivity of heavily doped polycrystalline silicon (poly-Si) on the doping concentration and annealing conditions. The resistivity of As-doped poly-Si with equal sized grains depends on the annealing temperature when the doping concentration is less than 5×1020 cm-3. This dependence is related to As segregation to the grain boundaries; that is, more As segregates to the grain boundaries as the temperature decreases. When the doping concentration exceeds 5×1020 cm-3, the As concentration in the grain reaches saturation and remains almost constant with increasing temperature. This means that the solid solubility limit is insensitive to the annealing temperature, and the resistivity remains almost constant with increasing annealing temperature. The resistivity of B-doped poly-Si does not depend on the annealing temperature when the doping concentration is less than the solid solubility limit. This indicates that B does not segregate significantly at the grain boundaries. When the doping concentration exceeds the solid solubility limit, the resistivity depends on the annealing temperature, because the solid solubility limit of B depends significantly on the annealing temperature. The solubility limit of B in poly-Si increases from 6×1019 cm-3 at 800° C to 1.5×1020 cm-3 at 1100° C. We proposed an empirical model that explains the experimental data.

High-Performance Low Operation Power Transistor for 45nm Node Universal Applications

High-performance low operation power (LOP) transistors were developed for 45nm node universal applications. A high uniaxial strain and low resistance NiSi technique, enhanced by a slit under the slim and high Youngs modulus (YM) offset spacer covered with dual stress liner (DSL), were used for electron and hole mobility enhancement and parasitic resistance (Rsd) reduction. The junction profile was also carefully optimized for low leakage current. As a result of a 12% mobility improvement and a 30% Rsd reduction, enhancements of 19 and 14% and Ion(@Ioff= 5 nA/mum) of 620 and 830 muA/mum were achieved for NMOS at 0.85 and 1.0V, respectively. As a result of a 45% mobility improvement and a 25% Rsd reduction, the enhancements of 32 and 22% and Ion of 330 and 440 muA/mum were achieved for PMOS at 0.85 and 1.0V, respectively. These results are the best Ion-Ioff tradeoff characteristics among the recent LOP transistors

A comprehensive study of fully-silicided gates to achieve wide-range work function differences (0.91 eV) for high-performance CMOS devices

We propose new methods to control the work function (WF) of nickel-fully-silicided (Ni-FUSI) gates. We clarified the amounts of segregated dopants, the status at the dielectric surface, and the composition of NiSi to determine the WF of the gates. We demonstrated the segregation mechanism for n- and p-type dopants during the silicidation processes. The amount of dopants used is effective for achieving wide-range WF. Nitridation of the gate oxide surface impacts both the WF of p-type gates and the oxide reliability. The Ni content of NiSi also changes the WF. These methods can be used to simultaneously control the WFs. Based on these three origins, we should be able to achieve wide-range WF differences (0.91 eV), suitable for use in 45-nm node CMOS devices.

Segregation Coefficient of Boron and Arsenic at Polycrystalline Silicon / SiO2 Interface

We evaluated how the segregation coefficient of boron and arsenic at the polycrystalline silicon (polysilicon)/silicon dioxide (SiO 2 ) interface is reated to the polysilicon morphology (grain size and orientation). Although the polysilicon morphology of the polysilicon strongly depends on the oxidation temperature, the segregation coefficient of boron is temperature independent and has a value of 0.357. The segregation coefficient of arsenic, however, depends on the polysilicon morphology, and cannot be expressed with a single activation energy. When the morphology is fixed by high temperature annealing at 1100 o C, the segregation coefficient of arsenic for temperatures below 1100 o C is expressed with a single activation energy as m As =3.23×10 9 exp[- 1.97 (eV)/K B T]

Maximum Active Concentration of Ion-Implanted Phosphorus During Solid-Phase Epitaxial Recrystallization

In this paper, we showed that the maximum active P concentration of approximately 2 times10²⁰ cm^-3 exists during solid-phase epitaxial recrystallization (SPER). This maximum active concentration is close to the reported values for other active impurity concentrations during SPER. We introduced the concept of an isolated impurity that has no neighbor impurities with a certain lattice range. Assuming that impurities interact with three or four neighbor impurities, we can explain the activation phenomenon during SPER. According to our model, the isolated P concentration <i>N</i> _iso has a maximum value of approximately 2 times10²⁰ cm^-3 at a total impurity concentration of approximately 10²¹ cm^-3, and it decreases with a further increase in total impurity concentration. Deactivation occurs after the completion of SPER with increasing annealing time, and the active impurity concentration decreases with time but is always higher than the maximum diffusion concentration <i>N</i> _Diff _max. We also observed that <i>N</i> _Diff _max is independent of the annealing time despite nonthermal activation in the high-concentration region. We evaluated the dependence of <i>N</i> _Diff _max on annealing temperatures. We think that this <i>N</i> _Diff _max can be regarded as the electrical solid solubility <i>N</i> _Esol that the active impurity concentration reaches in thermal equilibrium. We observed the transient enhanced diffusion (TED) after the completion of SPER, and that, the deactivation process continues during and after TED, and the corresponding diffusion coefficient is still much higher than that in thermal equilibrium even after TED has finished, which suggests that the deactivation process releases point defects.

Dependence of Sheet Resistance of CoSi2 with Gate Length of 30 nm on Thickness of Titanium Nitride Capping Layer in Co-Salicide Process

Since the distribution of gate resistance using cobalt silicide (CoSi2) increases markedly for gate lengths of 30 nm or less, CoSi2 is now being replaced by NiSi. However, CoSi2 still has the advantages of a high thermal stability and a low degree of roughness at the interface between the silicide and silicon layers owing to the low degree of mismatch (1.2%) of between their lattice constants. We have achieved excellent sheet resistance (Rs) with a gate length Lg=30 nm by optimizing the thickness of a cobalt capping layer of titanium nitride. The results shows an abnormal Rs behavior, in which one σ of Rs increases with capping layer thickness in the range of 10–50 nm, while it decreases with increasing capping layer thickness in the range of 0–10 nm. Unlike the results of a previous report [K. Goto et al.: IEDM Tech. Dig., 1995, p. 449], the variation in the Rs with a gate length Lg=30 nm is small, even without a TiN capping layer thickness down to 5–10 nm. We suggest that the uniformity of Rs is determined by the thickness of the CoSi layer after selective etching and the titanium concentration in the CoSi layer for capping TiN thicknesses of 10–50 nm, while the uniformity is determined by the titanium concentration and the damage sustained during selective etching for TiN thickness of 0–10 nm. For this optimization, CoSi2 is applicable to the 65 nm node technology node or beyond.

Novel Stack-SIN Gate Dielectrics for High Performance 30 nm CMOS for 45 nm Node with Uniaxial Strained Silicon

Aggressively scaled 30nm gate CMOSFETs for 45nm node is reported. We successfully improved a higher drive current with keeping the short channel effect by Sigma shaped SiGe-source/drain (Sigma SiGe) structure using compressive-stressed liner. In addition, we developed novel stack-SIN gate dielectrics by using bis-tertiarybutylamino-silane (BTBAS)/NH3. Novel stack-SIN gate dielectrics show higher immunity to negative bias temperature instability (NBTI) and time-dependent dielectric breakdown (TDDB) lifetime compared with conventional plasma nitrided silicon dioxide. These characteristic are originated from its unique nitrogen profile. The nitrogen concentration is over 22% at the surface of the dielectric and it rapidly decreases to 1% at the interface with a substrate. A high performance 30 nm gate nMOSFET and pMOSFET were demonstrated with a drive currents of 1042 muA/mum and 602 muA/mum at Vd = 1 V / Ioff=100 nA/mum, respectively