K. Hosaka

High-Performance Low Operation Power Transistor for 45nm Node Universal Applications

High-performance low operation power (LOP) transistors were developed for 45nm node universal applications. A high uniaxial strain and low resistance NiSi technique, enhanced by a slit under the slim and high Youngs modulus (YM) offset spacer covered with dual stress liner (DSL), were used for electron and hole mobility enhancement and parasitic resistance (Rsd) reduction. The junction profile was also carefully optimized for low leakage current. As a result of a 12% mobility improvement and a 30% Rsd reduction, enhancements of 19 and 14% and Ion(@Ioff= 5 nA/mum) of 620 and 830 muA/mum were achieved for NMOS at 0.85 and 1.0V, respectively. As a result of a 45% mobility improvement and a 25% Rsd reduction, the enhancements of 32 and 22% and Ion of 330 and 440 muA/mum were achieved for PMOS at 0.85 and 1.0V, respectively. These results are the best Ion-Ioff tradeoff characteristics among the recent LOP transistors

A comprehensive study of fully-silicided gates to achieve wide-range work function differences (0.91 eV) for high-performance CMOS devices

We propose new methods to control the work function (WF) of nickel-fully-silicided (Ni-FUSI) gates. We clarified the amounts of segregated dopants, the status at the dielectric surface, and the composition of NiSi to determine the WF of the gates. We demonstrated the segregation mechanism for n- and p-type dopants during the silicidation processes. The amount of dopants used is effective for achieving wide-range WF. Nitridation of the gate oxide surface impacts both the WF of p-type gates and the oxide reliability. The Ni content of NiSi also changes the WF. These methods can be used to simultaneously control the WFs. Based on these three origins, we should be able to achieve wide-range WF differences (0.91 eV), suitable for use in 45-nm node CMOS devices.

Effects of Gate Line Width Roughness on Threshold-Voltage Fluctuation Among Short-Channel Transistors at High Drain Voltage

We have experimentally evaluated the effects of the gate line width roughness (LWR) on the electrical characteristics of scaled n-MOSFETs. A larger gate LWR enhances the fluctuation in the subthreshold leakage current in short-channel n-MOSFETs even when the average gate length is maintained. Consequently, suppressing the gate LWR effectively reduces the variability in the threshold voltage of the scaled n-MOSFETs for a high drain voltage.

Sub-30-nm FUSI CMOS Transistors Fabricated by Simple Method Without Additional CMP Process

We fabricated sub-30-nm fully silicide (FUSI) CMOS transistors by a simple method without additional chemical-mechanical-polish and gate-capping-layer processes. The FUSI draped with source/drain (S/D) capping layer (D-FUSI) featuring shallow S/D Ni silicided layer without modulation of geometric structures is suitable to improve electrical characteristics of the short-channel transistor. Drive currents of 25-nm D-FUSI CMOS transistors increased by 15% more than those of the control.

Cost-effective Ni-melt-FUSI boosting 32-nm node LSTP transistors

We demonstrated for the first time that novel Ni-FUSI process using FLA (Melt-FUSI) dramatically improved both electrical characteristics and cost-benefit performance of LSTP devices. Since the T_inv was aggressively scaled (T_inv = 2.1 nm) with keeping SiON-gate leakage current and increasing hole mobility twice, we achieved the record I_on of 300 muA/mum at the I_off of 20 pA/mum for the pMOS transistor with the L_g of 45 nm at V_d of -1.2 V.

Study of Peeling at Doped NiSi/SiO2 Interface

The peeling of an impurity-doped NiSi film was investigated. We studied silicidation in detail and showed that its procedure varies depending on the doping site and dopant species used. The uneven crystal growth of NiSi causes the local consumption of polycrystalline silicon; thus voids form at the film interface NiSi/SiO2. These voids lead to film peeling. We also determined why the local consumption of polycrystalline silicon occurs. From the data we obtained, impurity may play a role in the local consumption of polycrystalline silicon.

High performance sub-35 nm bulk CMOS with hybrid gate structures of NMOS ; Dopant Confinement Layer (DCL) / PMOS ; Ni-FUSI by using Flash Lamp Anneal (FLA) in Ni-silicidation

We applied flash lamp annealing (FLA) in Ni-silicidation to our developed dopant confinement layer (DCL) structure for the first time. DCL technique is a novel stress memorization technique (SMT). We successfully improved the short channel effect (SCE) with keeping a high drive current by FLA in Ni-silicidation. For pMOSFET, 2 layers Ni fully-silicide (Ni-FUSI) was selectively formed on gates, and both effective work function (WF) control and thinner Teff are improved. On the other hand, unlike pMOS, Ni-FUSI process is not performed in nMOS. Both higher activation of halo and reduction of parasitic resistance in nMOSFET are improved by the combination of DCL structure and FLA in Ni-silicidation. Consequently, the higher drive currents of 1255 muA/mum and 759 muA/mum were obtained Ioff=122 nA/mum and 112 nA/mum at |Vdd|=1.0 V for nMOSFET and pMOSFET, respectively.

(110) NMOSFETs competitive to (001) NMOSFETs: Si migration to create (331) facet and ultra-shallow Al implantation after NiSi formation

We demonstrated for the first time the device performance of (110) nMOSFETs featuring a Si migration process, resulting in better mobility and modified shape of the narrow active region, and ultra-shallow Al implantation after nickel silicide (NiSi) formation, resulting in reduced parasitic resistance. We found that these processes made the performance of (110) nMOSFETs competitive with that of (001) nMOSFETs while maintaining their 40% advantage in pMOSFET performance.

Threshold Voltage Instability of 45-nm-node Poly-Si- or FUSI-Gated SRAM Transistors Caused by Dopant Lateral Diffusion in Poly-Si

Abstract We investigated lateral diffusion of dopants in gate poly-Si. The lateral diffusivity is approximately one order smaller than the diffusivity toward the vertical direction, but much larger than that in crystal Si. Simulation using the extracted diffusivities revealed serious problems in the threshold voltage shift (over 100mV) of SRAM transistors with poly-Si or fully-silicided (FUSI) gates. We experimentally confirmed this effect. Especially, the lateral diffusion much decreases static noise margin (SNM) of SRAM due to Vth fluctuation.