H. Fukutome

Direct Evaluation of Gate Line Edge Roughness Impact on Extension Profiles in Sub-50-nm n-MOSFETs

In this paper, the impact of gate line edge roughness (LER) on two-dimensional carrier profiles in sub-50-nm n-MOSFETs was directly evaluated. Using scanning tunneling microscopy (STM), it was clearly observed that the roughness of extension edges induced by gate LER strongly depended on the implanted dose, pockets, and coimplantations. Impurity diffusion suppressed by a nitrogen (N) coimplant enhanced the roughness of the extension edges, which caused fluctuations in the device performance. The expected effect based on the carrier profiles measured by STM of the N coimplant on the electrical performance of the n-MOSFETs was verified

Direct measurement of effects of shallow-trench isolation on carrier profiles in sub-50 nm N-MOSFETs

The effects of shallow-trench isolation (STI) on the carrier profile of the extension region in sub-50-nm n-MOSFET were directly measured for the first time. The extension overlap length drastically decreased by 3 run within a distance from STI (Y) of 50 nm. In contrast, the channel concentration gradually increased within Y of 100 nm. The STI effect was also measured for transistors with a gate width of less than 130 nm in 6T-SRAM cell. Reduction of the STI effect by nitrogen co-implant suppressed sub-threshold leakage current by up to an order of magnitude and decreased fluctuation in the threshold voltage by 8 %.

Direct evaluation of gate line edge roughness impact on extension profiles in sub-50nm N-MOSFETs

We directly evaluated the impact of gate line edge roughness (LER) on two-dimensional carrier profiles in sub-50-nm n-FETs. Using scanning tunneling microscopy, we clearly observed that the roughness of the extension edges induced by the gate LER strongly depended on the implanted dose, pockets, and co-implantations. Impurity diffusion suppressed by a nitrogen (N) co-implant enhanced the roughness of the extension edges, which caused fluctuation in the device performance. We verified the expected impact of the N co-implant on the electrical performance of the n-FETs.

Suppression of Poly-Gate-Induced Fluctuations in Carrier Profiles of Sub-50nm MOSFETs

We have investigated what effects randomly oriented and rotated poly-Si gate grains have on lateral carrier profiles in sub-50-nm MOSFETs by direct observations and electrical measurements. Since amorphous gates suppress random channeling penetration of pocket implants, we have increased effective mobility (40%), improved Vth roll-off characteristic (7 nm) and decreased Vth fluctuation (-26%)

High-Performance Low Operation Power Transistor for 45nm Node Universal Applications

High-performance low operation power (LOP) transistors were developed for 45nm node universal applications. A high uniaxial strain and low resistance NiSi technique, enhanced by a slit under the slim and high Youngs modulus (YM) offset spacer covered with dual stress liner (DSL), were used for electron and hole mobility enhancement and parasitic resistance (Rsd) reduction. The junction profile was also carefully optimized for low leakage current. As a result of a 12% mobility improvement and a 30% Rsd reduction, enhancements of 19 and 14% and Ion(@Ioff= 5 nA/mum) of 620 and 830 muA/mum were achieved for NMOS at 0.85 and 1.0V, respectively. As a result of a 45% mobility improvement and a 25% Rsd reduction, the enhancements of 32 and 22% and Ion of 330 and 440 muA/mum were achieved for PMOS at 0.85 and 1.0V, respectively. These results are the best Ion-Ioff tradeoff characteristics among the recent LOP transistors

Effects of Gate Line Width Roughness on Threshold-Voltage Fluctuation Among Short-Channel Transistors at High Drain Voltage

We have experimentally evaluated the effects of the gate line width roughness (LWR) on the electrical characteristics of scaled n-MOSFETs. A larger gate LWR enhances the fluctuation in the subthreshold leakage current in short-channel n-MOSFETs even when the average gate length is maintained. Consequently, suppressing the gate LWR effectively reduces the variability in the threshold voltage of the scaled n-MOSFETs for a high drain voltage.

Novel Thin Sidewall Structure for High Performance Bulk CMOS with Charge-Assisted Source-Drain-Extension

We have developed a novel junction profile engineering using thin sidewall structure and applied it to sub-40 nm uniaxial strained CMOS devices. This transistor used a high-k thin sidewall with electrical charge in achieving a higher drive current with keeping the short channel effect. Consequently, the 18.5/15.6% reduction of parasitic resistance achieve the 8.2/13.0% improvement in the saturation current (Ion) at 38 nm gate length for nMOS and pMOS. In addition, Ion dependence on active width (Wg) for pMOS is very small. In the size of active width : 0.1 mum, a 42% of Ion enhancement gave us Ion = 680 muA/mum at Vdd=1 V. These characteristics are originated from formation of inversion layer and suppressing channeling penetration of pocket impurities implanted. A high performance Bulk nMOS and pMOS were demonstrated with Ion of 1069 muA/mum and 725 muA/mum at Vdd=1 V / Ioff=100 nA/mum, respectively.

Integration Strategy of Embedded SiGe S/D CMOS from Viewpoint of Performance and Cost for 45nm-Node and Beyond

Direct comparison between competitive process flows showed that the eSiGe-S/D-last flow is the most promising CMOS integration process for manufacturing 45-nm technology node and beyond because it has good extensibility with various performance boosters, has fewer process steps and suppresses electrical fluctuations. The eSiGe-S/D-last (after offset spacer + I.I.) flow creates a sufficient process window that comprehensively optimizes both channel strain, induced by eSiGe-S/D (proximity, elevated height, and uniformity), and carrier profiles (offset spacer and thermal budget including millisecond annealing). An optimized eSiGe-S/D with a low thermal budget and amorphous Si gate decreases electrical fluctuations resulting in continuous scaling and a lower manufacturing cost.

Sub-30-nm FUSI CMOS Transistors Fabricated by Simple Method Without Additional CMP Process

We fabricated sub-30-nm fully silicide (FUSI) CMOS transistors by a simple method without additional chemical-mechanical-polish and gate-capping-layer processes. The FUSI draped with source/drain (S/D) capping layer (D-FUSI) featuring shallow S/D Ni silicided layer without modulation of geometric structures is suitable to improve electrical characteristics of the short-channel transistor. Drive currents of 25-nm D-FUSI CMOS transistors increased by 15% more than those of the control.

Fluorine implantation impact in extension region on the electrical performance of sub-50nm P-MOSFETs

We conclude that fluorine implantation in the extension region (F-tub) makes the Vth roll-off characteristic dramatically improve without degrading the drive current. Using scanning tunneling microscopy (STM) for two-dimensional (2D) carrier profiling, we directly confirmed that such an improvement of the device performance was induced by the reduction of the overlap length and the steep lateral abruptness on the nanometer scale.