Kazutaka Kasuga

An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM

This paper presents a three-dimensional (3D) system integration of a commercial processor and a memory by using inductive coupling. A 90nm CMOS 8-core processor, back-grinded to a thickness of 50µm, is mounted face down on a package by C4 bump. A 65nm CMOS 1MB SRAM of the same thickness is glued on it face up, and the power is provided by conventional wire-bonding. The two chips under different supply voltages are AC-coupled by inductive coupling that provides a 19.2Gb/s data link. Measured power and area efficiency of the link is 1pJ/b and 0.15mm2/Gbps, which is 1/30 and 1/3 in comparison with the conventional DDR2 interface respectively [1]. The power efficiency is improved by narrowing a transmission data pulse to 180ps. Reduced timing margin for sampling the narrow pulse, on the other hand, is compensated against timing skews due to layout and PVT variations by a proposed 2-step timing adjustment using an SRAM through mode. All the bits of the SRAM is successfully accessed with no bit error under changes of supply voltages (±5%) and temperature (25°C, 55°C).

An 8Tb/s 1pJ/b 0.8mm 2 /Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM

This paper presents an 8Tb/s 1pJ/b 0.8mm2/Tb/s quad data rate (QDR) inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM. The interface consists of 1024-bit parallel inductive-coupling transceivers operating at 8Gb/s/link. In the DRAM transceiver, data are multiplexed and demultiplexed by using a quadrature clock and XOR operation. This circuit technique for QDR compensates for transistor performance gap between the GPU and the DRAM to achieve 8Gb/s bandwidth. The clock for data retiming is recovered from the received data by using an injection-lock VCO. Clock links and clock distribution circuits are not needed, resulting in small layout area of 0.8mm2/Tb/s. Frontend of the transceiver is implemented using NMOS CML circuits with adaptive bias control. The transceivers sensitivity to PVT variations is small, enabling all the 1024 parallel transceivers to operate at BER≪10{−16}. It also reduces the design margin required of the transceiver, resulting in power reduction to 1pJ/b. Compared to the latest wired 40nm DRAM interface [1], the bandwidth is 32x higher, while the energy consumption is 1/8 and the layout area is 1/22.

MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link

MuCCRA-Cube is a scalable three dimensional dynamically reconfigurable processor. By stacking multiple dies connected with inductive-coupling links, the number of PE array can be increased so that the required performance is achieved. A prototype chip with 90nm CMOS process consisting of four dies each of which has a 4 × 4 PE array was implemented. The vertical link achieved 7.2Gb/s/chip, and the average execution time is reduced to 31% compared to that using a single chip.

3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link

This paper describes a three-dimensional (3-D) system integration of a full-fledged processor chip and two memory chips using inductive coupling. To attain a 3-D communication link with a smaller area and lower power-consumption, shortening the link distance and preventing signal degradation due to unused inductors are important challenges. Therefore, we developed a new 3D-integrated wire-penetrated multi-layer structure for a shorter link distance and an open-skipped-inductor scheme for suppressing signal degradation. In addition, to avoid undefined-value propagation in stacking multi-memories using an inductive-coupling link, we proposed a memory-access-control scheme with a pinpoint-data-capture scheme. We demonstrate that three fabricated chips can be successfully AC-coupled using inductive coupling. The power and area efficiency of the link are 1 pj/b and 0.15 mm2 /Gbps, respectively, which are the same as those of two-chip integration.

An extended XY coil for noise reduction in inductive-coupling link

Inductive-coupling link between stacked chips in a package communicates by using coils made by on-chip interconnections. An XY-coil layout style allows logic interconnections to go through the coil, which significantly saves interconnection resources consumed by the coil. However, the logic interconnections generate capacitive-coupling noise on the coil and degrade signal in the inductive-coupling link. In this paper, an extended XY coil with ground shields is presented for noise reduction. Simulation study shows that the noise voltage is reduced to 1/5 of the conventional XY coil. This noise reduction enables to reduce transmit power required for the same BER. Test-chip measurement in 0.18μm CMOS demonstrates that the transmit power at lGb/s with BER<10-12 is reduced by 60% compared to the conventional XY coil.

Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration

Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip links for 3-D system integration is introduced for the first time. Misalignment between stacked chips reduces coupling coefficiency of on-chip inductors and increases transmitter power. We proposed a modeling which estimates the increase in transmitter power by considering misalignment as an additional communication distance. Proposed model was verified by electromagnetic simulations and by measurements using testchips fabricated in 65-nm CMOS technology. The results calculated by the proposed modeling match well with measurement results. Measurement results show that misalignment tolerance of inductive-coupling link is well high and can be ignored in common conditions.

A Wafer test method of inductive-coupling link

This paper provides the method for Wafer test of an inductive-coupling link. The inductive-coupling link can be tested whether it operates correctly before stacking chips. We provided the method that verify the operation of an inductive-coupling link from the relation between coupling coefficient of inductors and power that transmitter consumes.