Yasufumi Sugimori

An 11Gb/s Inductive-Coupling Link with Burst Transmission

An inductive-coupling link is presented whose data rate is 11Gb/s for a distance of 15mum and 8.5Gb/s for a distance of 45mum. The data rate is increased by 11 to 8.5x over past inductive-coupling links. Compared with the capacitive-coupling link (Cu et al., 2007), the communication distance is extended by 5x for the same data rate, layout area, and bit error rate (BER), even by using a less- scaled device technology, 0.18mum CMOS.

An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM

This paper presents a three-dimensional (3D) system integration of a commercial processor and a memory by using inductive coupling. A 90nm CMOS 8-core processor, back-grinded to a thickness of 50µm, is mounted face down on a package by C4 bump. A 65nm CMOS 1MB SRAM of the same thickness is glued on it face up, and the power is provided by conventional wire-bonding. The two chips under different supply voltages are AC-coupled by inductive coupling that provides a 19.2Gb/s data link. Measured power and area efficiency of the link is 1pJ/b and 0.15mm2/Gbps, which is 1/30 and 1/3 in comparison with the conventional DDR2 interface respectively [1]. The power efficiency is improved by narrowing a transmission data pulse to 180ps. Reduced timing margin for sampling the narrow pulse, on the other hand, is compensated against timing skews due to layout and PVT variations by a proposed 2-step timing adjustment using an SRAM through mode. All the bits of the SRAM is successfully accessed with no bit error under changes of supply voltages (±5%) and temperature (25°C, 55°C).

2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking

A wireless communication technique, which enables a controller chip to communicate with random access with a stack underneath it of 64 NAND Flash memory chips at a data rate of 2Gb/s using relayed transmission is developed (Fig. 13.5.1). This technique can be applied to memory access in solid-state drives (SSD). The wireless interface allows the removal of a highly capacitive ESD protection device and results in a 2× reduction in power consumption, and a 40× reduction in I/O circuit-layout area. Using bonding wires for the power supply and wireless interface for data access reduces the number of bonding wires in the 64-chip stack from over 1,500 wires to less than 200 wires. This reduction in the number of bonding wires makes it possible to integrate 64 chips in one package, which conventionally requires eight separate packages. This wireless interface is based on inductive coupling between inductors on the stacked chips. The inductors emit magnetic field both upwards and downwards. This creates both intentional and unintentional communication link, which makes it difficult to be used in homogeneous stacking. Our technique enables data delivery upwards and downwards for memory read and write with measured BER ≪ 10–12. Power reduction is achieved by proper state programming of individual chips.

MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link

MuCCRA-Cube is a scalable three dimensional dynamically reconfigurable processor. By stacking multiple dies connected with inductive-coupling links, the number of PE array can be increased so that the required performance is achieved. A prototype chip with 90nm CMOS process consisting of four dies each of which has a 4 × 4 PE array was implemented. The vertical link achieved 7.2Gb/s/chip, and the average execution time is reduced to 31% compared to that using a single chip.

3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link

This paper describes a three-dimensional (3-D) system integration of a full-fledged processor chip and two memory chips using inductive coupling. To attain a 3-D communication link with a smaller area and lower power-consumption, shortening the link distance and preventing signal degradation due to unused inductors are important challenges. Therefore, we developed a new 3D-integrated wire-penetrated multi-layer structure for a shorter link distance and an open-skipped-inductor scheme for suppressing signal degradation. In addition, to avoid undefined-value propagation in stacking multi-memories using an inductive-coupling link, we proposed a memory-access-control scheme with a pinpoint-data-capture scheme. We demonstrate that three fabricated chips can be successfully AC-coupled using inductive coupling. The power and area efficiency of the link are 1 pj/b and 0.15 mm2 /Gbps, respectively, which are the same as those of two-chip integration.

Interference from power/signal lines and to SRAM circuits in 65nm CMOS inductive-coupling link

This paper discusses interference of an inductive-coupling link in 65nm CMOS. Electromagnetic interference from power/signal lines and to SRAM was simulated and measured. Interference from power lines for mobile applications (line and space) is smaller than that for high-performance applications (mesh type). Interference from signal lines requires only 9% of additional transmit power even in the worst case of logic circuits. In typical operation range, interference to SRAM is ignorable. Only when supply voltage is much lower than typical range, the bit-line noise from the inductive-coupling link influences SRAM operation. Interference to SRAM is small compared with other influences such as device variations and soft errors.

47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking

This paper presents a power reduction scheme and an area reduction scheme in inductive-coupling programmable bus for NAND flash memory stacking. A channel arrangement scheme using three coils enables random access for memory read and memory write. Transmit power is reduced by 47% compared to a previous design with shields. A coil layout style, herein noted as XY coil, allows for the coils to interleave with logic interconnections, resulting in area reduction of 91% relative to at the expense of only 17% transmit power increase. Relayed data transmission at 1.6 Gb/s and BER <; 10-12 is achieved.

Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration

Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip links for 3-D system integration is introduced for the first time. Misalignment between stacked chips reduces coupling coefficiency of on-chip inductors and increases transmitter power. We proposed a modeling which estimates the increase in transmitter power by considering misalignment as an additional communication distance. Proposed model was verified by electromagnetic simulations and by measurements using testchips fabricated in 65-nm CMOS technology. The results calculated by the proposed modeling match well with measurement results. Measurement results show that misalignment tolerance of inductive-coupling link is well high and can be ignored in common conditions.

Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for 3D System Integration

for 3D System Integration Kiichi Niitsu, Yoshinori Kohama, Yasufumi Sugimori, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro and Tadahiro Kuroda Keio University, Department of Electronics and Electrical Engineering 3-14-1, Hiyoshi, Kohoku-ku, Yokohama 223-8522, Japan Phone: +81-45-566-1779, E-mail: {kiichi, kohama, sugimori}@kuro.elec.keio.ac.jp, {ishikuro, kuroda}@elec.keio.ac.jp Hitachi Central Research Laboratory, Kokubunji, 185-8601, Japan

Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration

This paper discusses analysis and techniques for mitigating interference of an inductive-coupling inter-chip link. Electromagnetic interference from power/signal lines and to SRAM circuits was simulated and measured. In order to verify the interference, test chips were designed and fabricated using 65-nm CMOS technology. The measurement results revealed that: 1) interference from power lines depends on the shape of the power lines; 2) interference from signal lines can be canceled by increasing transmitter power by only 9%; and 3) interference with SRAM circuits is less important than other issues under ordinary conditions. Based on the measurement results, interference mitigation techniques are proposed and investigated.