Mitsuko Saito

2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking

A wireless communication technique, which enables a controller chip to communicate with random access with a stack underneath it of 64 NAND Flash memory chips at a data rate of 2Gb/s using relayed transmission is developed (Fig. 13.5.1). This technique can be applied to memory access in solid-state drives (SSD). The wireless interface allows the removal of a highly capacitive ESD protection device and results in a 2× reduction in power consumption, and a 40× reduction in I/O circuit-layout area. Using bonding wires for the power supply and wireless interface for data access reduces the number of bonding wires in the 64-chip stack from over 1,500 wires to less than 200 wires. This reduction in the number of bonding wires makes it possible to integrate 64 chips in one package, which conventionally requires eight separate packages. This wireless interface is based on inductive coupling between inductors on the stacked chips. The inductors emit magnetic field both upwards and downwards. This creates both intentional and unintentional communication link, which makes it difficult to be used in homogeneous stacking. Our technique enables data delivery upwards and downwards for memory read and write with measured BER ≪ 10–12. Power reduction is achieved by proper state programming of individual chips.

An 8Tb/s 1pJ/b 0.8mm 2 /Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM

This paper presents an 8Tb/s 1pJ/b 0.8mm2/Tb/s quad data rate (QDR) inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM. The interface consists of 1024-bit parallel inductive-coupling transceivers operating at 8Gb/s/link. In the DRAM transceiver, data are multiplexed and demultiplexed by using a quadrature clock and XOR operation. This circuit technique for QDR compensates for transistor performance gap between the GPU and the DRAM to achieve 8Gb/s bandwidth. The clock for data retiming is recovered from the received data by using an injection-lock VCO. Clock links and clock distribution circuits are not needed, resulting in small layout area of 0.8mm2/Tb/s. Frontend of the transceiver is implemented using NMOS CML circuits with adaptive bias control. The transceivers sensitivity to PVT variations is small, enabling all the 1024 parallel transceivers to operate at BER≪10{−16}. It also reduces the design margin required of the transceiver, resulting in power reduction to 1pJ/b. Compared to the latest wired 40nm DRAM interface [1], the bandwidth is 32x higher, while the energy consumption is 1/8 and the layout area is 1/22.

A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stacking

128 NAND Flash memory chips and 1 controller chip are stacked in a single package for SSD applications (Fig. 24.5.1). The controller chip accesses a random memory chip by relayed transmission using inductive-coupling transceivers [1,2]. A conventional terraced chip stacking scheme [1] requires spacer chips to provide bonding space. The total height would be 6.0mm. A spiral stair stacking scheme is proposed that requires no spacer chips. The total height is reduced to 3.9mm. Average communication distance is shortened, and transmission power is reduced to 60%. A coil of 1.1mm diameter, larger than conventional, is employed to extend the communication distance for enabling transmission relayed at every 8th chip. Number of transceivers activated for chip access is reduced to ¼ compared to [1,2] where transmission was relayed at every 2nd chip with a coil of 0.2mm diameter. Although the transmission power needs to be increased by 3x in order to compensate for signal degradation due to eddy current, the transmission power is still reduced to 60% × (¼) × 3 =45%. Together with the reduction of the number of the activated receivers, energy consumption for the random access is reduced to 1.8pJ/b/chip which is 33% of [2]. The large coil is placed over memory core by using the third metal layer. Layout penalty is negligibly small, since the third metal is not utilized over the memory core other than reinforcing power supply in source lines. By placing the square coil diagonally to bit/word lines, capacitive/inductive interference between the chip access and memory read/write can be significantly reduced.

A 2.7Gb/s/mm 2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stacking

This paper presents an inductive-coupling interface for NAND Flash memory stacking whose bandwidth per unit area is 2.7Gb/s/mm2 and energy consumption per chip is 0.9pJ/b/chip. The bandwidth is increased by 10× (in other words, layout area is reduced to 1/10 for the same data rate), and the energy consumption is reduced by half, both compared to the latest research results [1]. A relayed transmission scheme using one coil is proposed to reduce the number of coils in a data link. Coupled resonation is utilized for clock and data recovery (CDR) for the first time in the world, resulting in elimination of a source synchronous clock link. As a result, total number of coils needed to form a channel is reduced from 6 to 1, yielding the significant improvement in data rate, layout area and energy consumption.

A 1 TB/s 1 pJ/b 6.4

1 TB/s 1 pJ/b 6.4 mm2 /TB/s QDR inductive-coupling interface between 65-nm complementary metal-oxide-semicon ductor (CMOS) logic and emulated 100-nm dynamic random access memory (DRAM) is developed. BER <;10-10 operation is examined in 1024-bit parallel links. Compared to the latest wired 40-nm DRAM interface, the bandwidth is increased to 32×, and the energy consumption and the layout area are reduced to 1/8 and 1/22, respectively.

{\rm mm}^{2}/{\rm TB/s}

This paper presents a power reduction scheme and an area reduction scheme in inductive-coupling programmable bus for NAND flash memory stacking. A channel arrangement scheme using three coils enables random access for memory read and memory write. Transmit power is reduced by 47% compared to a previous design with shields. A coil layout style, herein noted as XY coil, allows for the coils to interleave with logic interconnections, resulting in area reduction of 91% relative to at the expense of only 17% transmit power increase. Relayed data transmission at 1.6 Gb/s and BER <; 10-12 is achieved.

QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM

Inductive-coupling link between stacked chips in a package communicates by using coils made by on-chip interconnections. An XY-coil layout style allows logic interconnections to go through the coil, which significantly saves interconnection resources consumed by the coil. However, the logic interconnections generate capacitive-coupling noise on the coil and degrade signal in the inductive-coupling link. In this paper, an extended XY coil with ground shields is presented for noise reduction. Simulation study shows that the noise voltage is reduced to 1/5 of the conventional XY coil. This noise reduction enables to reduce transmit power required for the same BER. Test-chip measurement in 0.18μm CMOS demonstrates that the transmit power at lGb/s with BER<10-12 is reduced by 60% compared to the conventional XY coil.

47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking

This paper provides the method for Wafer test of an inductive-coupling link. The inductive-coupling link can be tested whether it operates correctly before stacking chips. We provided the method that verify the operation of an inductive-coupling link from the relation between coupling coefficient of inductors and power that transmitter consumes.

An extended XY coil for noise reduction in inductive-coupling link

An asynchronous pulse transmitter is proposed to achieve low power in inductive-coupling link. The conventional asynchronous transmitter, H-bridge inductive-coupling transmitter, consumes large static (DC) current consumption. Therefore the transmit power dissipation is dominant in the total inductive-coupling power dissipation. The proposed pulse inductive-coupling transmitter eliminates the static (DC) current consumption. It provides linear power scalability which significantly reduces the power consumption especially at low data rate operation for low-power mobile applications. To verify the proposed technique, we designed and fabricated test chips in TSMC 0.18 µm complementary metal oxide semiconductor (CMOS) technology. Both proposed pulsed transmitter and conventional H-bridge transmitter is implemented in the test chip for comparison. Power reduction to 1/4 at 1.5 Gbps and 1/60 at 100 Mbps is achieved compared to the conventional transmitter. Also a crosstalk immune inductive-coupling receiver is presented for low-power relayed transmission using the proposed pulse transmitter. Crosstalk guard circuit is implemented in the receiver to ignore crosstalk. Data is successfully transferred using relayed transmission with proposed transceiver at up to 400 Mbps.

A Wafer test method of inductive-coupling link

Memory cards are widely used in electronic systems to expand internal storage area or are used as detachable media to carry data. Although cloud computing has recently drawn attention, data transfer consumes significant power (e.g., 1% battery charge of a smartphone when 10 pictures are transferred through WLAN), making local memory card storage still attractive in mobile devices. As storage capacity increases, the I/O speed should also increase accordingly. However, conventional memory cards require strong ESD protection, limiting high-speed data transfer. A non-contact memory card [1] is one of the solutions to this problem. No signal terminals are exposed for mechanical contact, which relaxes ESD constraints. A data transfer rate of 6Gb/s/ch by inductive coupling [1] and 12Gb/s/ch by transmission-line coupling [2] are reported. The post-UHS-II speed over 5Gb/s can be covered with around 10mW power consumption. Moreover, by supplying power wirelessly, mechanical connections can be completely removed, which could provide features such as waterproof capability or a new attach-remove user interface. A >50% high-efficient wireless power delivery has been reported [3]. However, it mainly supplies a large amount of active power, and the efficiency drops to ~10% in low-power standby mode. Shutting down the power delivery in standby would require a power-on sequence and an unacceptably long suspend (~10s) for each new command. For high-speed card access, the power delivery and the wireless data receiver (RX) should always be active, consuming about 2mW in RX and in total 20mW including loss in the wireless power delivery. This standby power is almost identical to that of typical smartphones, tablet-PCs, or camcorders and the battery life halves.