Kazuyasu Fujishima

Twisted bit-line architectures for multi-megabit DRAMs

As the memory cell array of DRAM has been scaled down, inter-bit-line coupling noise has emerged as a serious problem. The signal loss due to this noise is estimated at about 40% of the signal amplitude in a polycide-bit-line 16-Mb DRAM with a technologically attainable scaling scheme. Twisted bit-line architectures to reduce or eliminate the noise are proposed and demonstrated by the soft-error rate improvement of a 1-Mb DRAM. The effective critical charge is improved by 35%, which is attributed not only to the improvement of the signal amplitude but also to the elimination of large coupling noise during the sensing operation. The impact of these twisted bit-line architectures from a scaling viewpoint is also examined, and they are shown to be promising candidates for overcoming the scaling problems of DRAMs. >

The cache DRAM architecture: a DRAM with an on-chip cache memory

A DRAM (dynamic RAM) with an on-chip cache, called the cache DRAM, has been proposed and fabricated. It is a hierarchical RAM containing a 1-Mb DRAM for the main memory and an 8-kb SRAM (static RAM) for cache memory. It uses a 1.2- mu m CMOS technology. Suitable for no-wait-state memory access in low-end workstations and personal computers, the chip also serves high-end systems as a secondary cache scheme. It is shown how the cache DRAM bridges the gap in speed between high-performance microprocessor units and existing DRAMs. The cache DRAM concept is explained, and its architecture is presented. The error checking and correction scheme used to improve the cache DRAMs reliability is described. Performance results for an experimental device are reported.<<ETX>>

A 34-ns 16-Mb DRAM with controllable voltage down-converter

A high-speed 16-Mb DRAM with high reliability is reported. A multidivided column address decoding scheme and a fully embedded sense-amplifier driving scheme were used to meet the requirements for high speed. A low-power hybrid internal power supply voltage converter with an accelerated life-test function is also proposed and was demonstrated. A novel substrate engineering technology, a retrograded well structure formed by a megaelectronvolt ion-implantation process, provides a simple process sequence and high reliability in terms of soft error and latch-up immunity. >

A new multilevel storage structure for high density CCD memory

A multilevel storage (MLS) structure for high density CCD memory is proposed and demonstrated. Using four levels of charge, 2 bits can be stored in one storage cell. Stored charge is transferred by a clocking scheme which provides larger charge-carrying capacity without increasing memory cell size. These techniques make it possible to achieve high packing density without requiring fine patterning.

A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode

To realize an efficient redundancy test using the multibit test (MBT) mode, a redundancy flag on a memory LSI tester and an effective redundancy technique which cooperates with the MBT mode have been introduced. This simple redundancy architecture needs only the RFLG (512 bits for the 1 M*1-bit DRAM) as a hardware option on a memory LSI tester. The program development time for the redundancy test has been shortened. Throughput improvement of six to ten times has been achieved in the actual 1-Mb DRAM redundancy test. >

A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register

A single 3.3-V 16-Mbit DRAM with a 135-mm/sup 2/ chip size has been fabricated using a 0.5- mu m twin-well process with double-metal wiring. The array architecture, based on the twisted-bit-line (TBL) array, includes suitable dummy and space word-line configurations which suppress the inter-bit-line noise and bring yield improvement. The multipurpose register (MPR) designed for the hierarchical data bus structure provides a line-mode test (LMT), copy write, and cache access capability. The LMT with on-chip test circuits using the MPR and a comparator creates a random test pattern and reduces the test time to 1/1000. A field shield isolation and a T-shaped stacked capacitor allow the layout of a 4.8- mu m/sup 2/ cell size with a storage capacitance of 35 fF. These techniques enable the 3.3-V 16-Mbit DRAM to achieve a 60-ns RAS access time and 300-mW power dissipation at 120-ns cycle time. >

Cell-plate line connecting complementary bit-line (C/sup 3/) architecture for battery-operated DRAMs

In low-voltage operating DRAMs, one of the most serious problems is how to maintain sufficient charge stored in the memory cell, which is concerned with the operating margin and soft error immunity. An array architecture called the cell-plate line connecting complementary bit-line (C/sup 3/) architecture, which realizes a large signal voltage on the bit-line pair and low soft error rate (SER) without degrading the reliability of the memory cell capacitor dielectric film, is proposed. This architecture requires no unique process technology and no additional chip area. With the test device using the 16-Mb DRAM process, a 130-mV signal voltage is observed at 1.5-V power supply with 1.6- mu m*3.2- mu m cell size. This architecture should open the path for the future battery-backup and/or battery-operated high-density DRAMs. >

A new array architecture for parallel testing in VLSI memories

The authors describe a novel array architecture and its application to a 16-Mb DRAM (dynamic random-access memory) suitable for the line mode test (LMT) with test circuits consisting of a multipurpose register (MPR) and a comparator. The LMT can test all memory cells connected to a word line simultaneously. Testing with random patterns along a word line is easily realized by using the MPR as a pattern register after setting random test data in the MPR. Test time is reduced to approximately 1/1000. Owing to the MPR, the present LMT can achieve flexible testing with high fault coverage. The excess area penalty due to the circuits for the LMT is suppressed within 0.5% in application to the 16-Mb DRAM.<<ETX>>

Semiconductor memory device with a laser programmable redundancy circuit

A semiconductor memory device with a laser programmable redundancy circuit, which includes: a plurality of decoders for selecting a row or column of the memory; at least one spare decoder which is selected instead of a decoder connected to a faulty memory cell; a link element inserted in series with the precharging transistor and connected between the power supply and the decoder output line; a signal generator which generates a non-selection signal for making the object decoder unselected only when a spare decoder is selected, the signal generator being provided in the spare decoder; and a transistor, having a gate to which the non-selection signal is input, with the drain and the source thereof being connected to the decoder output and ground, respectively, the transistor being provided in the decoder.

A speed-enhanced DRAM array architecture with embedded ECC

An array architecture with countermeasures for the smaller signal charge caused by scaling down is proposed. Based on a new access model, the combination of a hierarchical data bus configuration and multipurpose register (MPR) provides high-speed array access. The MPR also includes practical array-embedded error checking and correcting (ECC) with little area penalty and no access overhead in the page mode. The array architecture is applied to a scaled-down 16-Mb DRAM and has achieved high performance. >