Kedar Sapre

Process Integration Considerations for 300 mm TSV Manufacturing

Through-silicon via (TSV) will transition to high volume production when end-customer value (as exhibited by functionality, performance, form factor, etc.) are delivered at equivalent yield and cost. While this has been successfully achieved for CMOS image sensors (starting with 200 mm), significant work remains to be done in the TSV value chain (design-materials-process-packaging-test) in the communication and memory segments. This paper will address key unit process/process-integration challenges and highlight recent internal/ partner and industry findings in the context of TSV manufacturability at 300 mm.

Robust TSV via-middle and via-reveal process integration accomplished through characterization and management of sources of variation

An overview is given of developments in unit-process and process-integration technology enabling the realization of through-silicon vias (TSVs) for 3D chip stacking. TSVs are expected to increase interconnect bandwidth, reduce wire delay due to shorter vertical signal path, and improve power efficiency [1-3]. The fabrication sequences for forming TSVs in the middle of the line (via-middle approach) and for revealing them from the backside in the far back end of the line are described with detailed attention to major unit processes of etch, dielectric deposition, barrier and seed deposition, electrochemical deposition, and chemical-mechanical planarization. Unit-process advances are described in relation to the structural and functional requirements of the TSVs, and examples are given of co-optimization among the interdependent steps of the integrated sequence. Emphasis is given to copper vias of diameter 4 to 10μm with aspect ratio between 8 and 12. For both the viaformation and via-reveal sequence, it is shown how integration problems were overcome by a comprehensive approach.

Material, Process and Geometry Effects on Through-Silicon Via Reliability and Isolation

Through-silicon via (TSV) structures with various material and geometry configurations are assessed to study their impact on reliability, isolation and performance. Oxide liner insulators show a larger performance impact as compared to low-k liners and the effect decreases with increasing liner insulator thickness. Higher density of the TSV array causes greater stress impact on carrier mobility and increases the parasitic capacitance. Additionally, low-k liner reduces the parasitic capacitance, but exhibits lower strength and adhesion, therefore degraded reliability. These results provide an important perspective of performance and reliability trade-offs necessary for a robust TSV design.

Through-silicon-via technology for 3D integration

Major efforts are currently underway throughout the IC industry to develop the capability to integrate device chips by stacking them vertically and using through-silicon vias (TSVs). The resulting interconnect density, bandwidth, and compactness achievable by TSV technology exceed what is currently possible by other packaging approaches. Market-driven applications of TSV involving memory include multi-chip high-performance DRAM, integration of memory and logic functions for enhanced video on handheld devices, and stacked NAND flash for solid-state drives. High-volume commercial implementation of 3D TSV is imminent but faced by special challenges of design, fabrication, bonding, test, reliability, know-good die, standards, logistics, and overall cost. The main focus of this paper is the unit-process and process-integration technology required for TSV fabrication at the wafer level: deep silicon etching, dielectric via isolation, metallization, metal fill, and chemical-mechanical polishing.