Keiji Mabuchi

A high-sensitivity CMOS image sensor with gain-adaptive column amplifiers

A high-sensitivity CMOS image sensor using gain-adaptive column amplifiers is presented and tested. The use of high gain for the column amplifier reduces input-referred random noise, and when coupled with a column-based digital noise cancellation technique, also reduces fixed pattern noise. An experimental application of the circuit using 0.25-/spl mu/m CMOS technology with pinned photodiodes gave an rms random noise of 263 /spl mu/V and an rms fixed pattern noise of 50 /spl mu/V.

A 1/4 inch 330 K square pixel progressive scan CMOS active pixel image sensor

CMOS active pixel sensors (APS) have attracted special attention in recent years because of monolithic integration of controlling, driving and signal processing circuitry within a single sensor chip. However, a large pixel area is required for implementing row select, charge reset and amplification elements in a pixel. Further pixel size shrinkage is necessary, especially for applications like consumer-use digital still photography. Reduced cell size is reported for the television, but the device operates only in the interlace scan mode. This consumer-use 1/4 inch 640(H)x480(V) pixel active pixel sensor has a 5.6x5.6/spl mu/m/sup 2/ pixel. The imager operates with a 5.0V single power supply and less than 30mW dissipation. The sensor uses 0.6/spl mu/m, double poly-silicon, triple-metal CMOS process technology.

A column-based pixel-gain-adaptive CMOS image sensor for low-light-level imaging

A 0.25 /spl mu/m technology CMOS image sensor employs a 4.2 /spl mu/m pitch pinned-photodiode pixel. A column amplifier and digital domain processing reduce the fixed pattern noise to 55 /spl mu/V. The saturation voltage is 1 V with a 2.5 V supply voltage, and the dynamic range is 69 dB.

CMOS image sensor using a floating diffusion driving buried photodiode

Two 2.5V VGA CMOS image sensors with 3.45/spl mu/m and 3.1/spl mu/m buried photodiode-pixels on a 0.25/spl mu/m 2P3M CMOS technology are described. The test chips utilize a floating diffusion driving technique to achieve 3-transistors/pixel and 2-transistors/pixel respectively, and operate at 60 frames/s with 49mW dissipation.

A 1/2.3-inch 10.3Mpixel 50frame/s Back-Illuminated CMOS image sensor

This paper presents a 1/2.3-inch 10.3Mpixel Back-Illuminated (BI) CMOS image sensor that targets both digital still camera (DSC) and high-definition camcorder applications. These applications require high-pixel-count, high-sensitivity, high saturation signal, low noise and high-speed imaging for image quality [1]. The sensor is scaled down to get a higher resolution due to higher pixel count. Several approaches such as a Cu process to reduce the pixel height and inner micro-lenses to gather rays of incident light have been proposed to overcome electro-optical challenges [2–4]. The BI process has been reported as one of the most promising technologies to improve optical performance [5,9]. This BI image sensor includes a 10b/12b analog-to-digital converter (ADC), an internal phase-locked loop (PLL) and a 10b serial LVDS interface to enable a data-rate up to 576MHz.

A 2/3-in 2 million pixel STACK-CCD HDTV imager

A 2/3-in optical format 2 M pixel STACK-CCD imager has been developed. The STACK-CCD imager, overlaid with an amorphous silicon photoconversion layer, realizes a large signal charge handling capability of 1.0/spl times/10/sup 5/ electrons, a -140 dB smear noise and a 90 dB dynamic range with a newly introduced device configuration and its unique operation. The 5.0 /spl mu/m(H)/spl times/5.2 /spl mu/m(V) unit pixel imager with sufficiently low image lag has been realized by a novel bias charge injection scheme These device performances are the best ever achieved by a CCD HDTV imager. This is the first such imager satisfying the device performances required for a practical use 2/3-in 2 M pixel HDTV imager. >