Masako Ohta

An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode

A 5-V 4M-word*4-b dynamic RAM (random-access memory) with a 100-MHz serial read/write mode using 0.7- mu m triple-tub CMOS technology is discussed. The RAM utilizes a recently developed STT (stacked trench capacitor) cell which achieved 37 fF in a small cell size of 1.7*3.6 mu m/sup 2/. The STD (sidewall transistor with double-doped drain) structure is used for PMOS-FETs to realize high-speed operation. To ensure MOSFET reliability, the 5-V external supply voltage is converted to a 4-V internal supply voltage by an on-chip voltage converter circuit. An on-chip interleaved circuit and double-input-buffer scheme is used to realize high-speed serial read/write operation. Using an external 5-V power supply, the RAM achieved a 100-MHz serial access cycle, and RAS access time is 70 ns. The typical active current is 120 mA at a 190-ns cycle time. >

New nibbled-page architecture for high-density DRAMs

A nibbled-page architecture which can be used to access all column addresses on the selected row address randomly in units of 8 bits at the 100 Mbit/s data rate is discussed. To realize such high-speed architecture, three key circuit techniques have been developed. An on-chip interleaved circuit has been used for the high-speed serial READ and WRITE operations. Column address prefetch and WE signal prefetch techniques have been introduced to eliminate idle time between 8 bit units. The nibbled-page architecture has been successfully implemented in an experimental 16 Mb DRAM, and 100 Mb/s operation has been achieved. The DRAM with nibbled-page mode is very effective in simplifying the design of high-speed data transfer systems. >

Variability aware modeling and characterization in standard cell in 45 nm CMOS with stress enhancement technique

Gate density is ultimately increased to 2100 kGates/mm2 by pushing the critical design rules without increasing the circuit margin in 45 nm technology. Layout dependences for stress enhanced MOSFET including contact positioning, 2nd neighboring poly effect, and bent diffusion are accurately modeled for the first time. With the constructed design flow, gate length change of -2.8% to +3.6% and Idsat change of -10% to +14% are removed from uncertain margin in 45 nm corner libraries.

An experimental DRAM with a NAND-structured cell

An experimental 256-Mb dynamic random access memory using a NAND-structured cell (NAND DRAM) has been fabricated. The NAND-structured cell has four memory cells connected in series, which reduces the area of isolation between the adjacent cells and also reduces the bit-line contact area. The cell area per bit measures 0.962 mu m/sup 2/, using 0.4- mu m CMOS technology, which is 63% in comparison with the conventional cell. In order to reduce the die size, time division multiplex sense-amplifier (TMS) architecture, in which a sense amplifier is shared by four bit lines, has been newly introduced. The chip area is 464 mm/sup 2/, which is 68% compared with the DRAM using the current cell structure. The data can be accessed by a fast-block-access mode up to 512 bytes as well as a random access mode. Typical 112-ns access time of the first data in a block and 30-ns serial cycle time are achieved. >

A 33-ns 64-Mb DRAM

A 64-Mb CMOS dynamic RAM (DRAM) measuring 176.4 mm/sup 2/ has been fabricated using a 0.4- mu m N-substrate triple-well CMOS, double-poly, double-polycide, double-metal process technology. The asymmetrical stacked-trench capacitor (AST) cells, 0.9 mu m*1.7 mu m each, are laid out in a PMOS centered interdigitated twisted bit-line (PCITBL) scheme that achieves both low noise and high packing density. Three circuit techniques were developed to meet high-speed requirements. Using the preboosted word-line drive-line technique, a bypassed sense-amplifier drive-line scheme, and a quasi-static data transfer technique, a typical RAS access time of 33 ns and a typical column address access time of 15 ns have been achieved. >

Layout Dependence Modeling for 45-nm CMOS With Stress-Enhanced Technique

Layout dependences for stress-enhanced MOSFETs including contact positioning, the second neighboring poly effect, and bent diffusion are modeled in 45-nm CMOS logic technology. It is found that the sensitivity of contact position in the channel direction is larger for PMOS with a higher stress liner than for NMOS. The effect of contact positions is modeled by using the distance of contact to gate (x) and the number of contacts (N). In terms of the gate-space effect, it is concluded that, in addition to the neighboring gates, second neighboring gates affect the channel stress. The effect of bent-shape diffusion is analyzed for NMOS and PMOS. For NMOS, the channel profile is affected by the bent shape. This can be described by the change of V th. For PMOS, the channel stress is modulated by the bent diffusion. The stress effect in bent-shape diffusion for PMOS is modeled with three geometrical parameters. The compact model is applied to the characterization of actual 45-nm cell libraries. It is confirmed that, with the constructed models and design flow, a saturation current (I dsat) change of -12%-14% is removed from the uncertain margin in 45-nm corner libraries.

A 0.5 V power-supply scheme for low power LSIs using multi-Vt SOI CMOS technology

Describes a novel power-supply scheme suitable for 0.5V operating LSIs. The system contains the on-chip buck dc-dc converter with over-90% efficiency, 0.5V operating logic, 100MHz operating F/Fs with holding data in the stand-by mode, and the dual-rail level converter. The dc-dc converter TEG, fabricated using 0.35/spl mu/m multi-Vt SOI CMOS process, realized stable recovery characteristics and a final stage efficiency of 92% with 0.5V/10mW output.

A 0.5-V power-supply scheme for low-power system LSIs using multi-V/sub th/ SOI CMOS technology

This paper proposes a novel power-supply scheme suitable for 0.5-V operating silicon-on-insulator (SOI) CMOS circuits. The system contains an on-chip buck DC-DC converter with over 90% efficiency, 0.5-V operating logic circuits, 100-MHz operating flip-flops at 0.5-V power supply, and level converters for the interface between the 0.5-V operating circuit and on-chip digital-to-analog (D/A) converters or external equipment. Based on the theory, the values of on-resistance and threshold voltage of SOI transistors are clarified for the 0.5-V/10-mW output DC-DC converter, which satisfies both high efficiency and low standby power. The proposed flip-flop can hold the data during the sleep with the use of the external power supply, while maintaining high performance during the active. The level converter comprises dual-rail charge transfer gates and a CMOS buffer with a cross-coupled nMOS amplifier to operate with high speed even in a conversion gain of higher than 6, where the conversion gain is defined as the ratio of the output and input signal swings. The test chip was fabricated for the 0.5-V power supply scheme by using multi-V/sub th/ SOI CMOS technology. The experimental results showed that the buck DC-DC converter achieved a conversion efficiency of 91% at 0.5-V/10-mW output with stable recovery characteristics from the sleep, and that the dual-rail level converter operated with a maximum data rate of 300 Mb/s with the input signal swing of 0.5 V.

A dual layer bitline DRAM array with Vcc/Vss hybrid precharge for multi-gigabit DRAMs

A dual layer BL array and a Vcc/Vss hybrid precharge sensing scheme has been proposed. The array affords the maximum memory cell density and relaxed sense amplifier layout which is as wide as the conventional folded BL sense amplifier layout. The Vcc/Vss hybrid precharge scheme gives the doubled operation voltage for sensing compared with the conventional half Vcc precharge method without the BL charge/discharge current increase.

A new reduced clock-swing flip-flop: NAND-type keeper flip-flop (NDKFF)

A new reduced clock-swing flip-flop, named NAND-type Keeper Flip-Flop (NDKFF) is proposed. Compared with other conventional reduced clock-swing flip-flops such as HSFF and RCSFF, NDKFF features a simple configuration, which does not have additional clock drivers or does not have additional nand/or p-wells. Compared with the hybrid-latch flip-flop, 52% of the flip-flop power and 64% of the clocking power are saved in the case of 0.25 /spl mu/m CMOS technology. Moreover CLK-to-Q delay is comparable to that of conventional C2MOS-type master-slave flip-flop.