Kenneth C. Marston

A Practical Implementation of Silicon Microchannel Coolers for High Power Chips

This paper describes a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors. Through the use of multiple heat exchanger zones and optimized cooler fin designs, a unit thermal resistance 10.5 C-mm2 /W from the cooler surface to the inlet water was demonstrated with a fluid pressure drop of <35kPa. Further, cooling of a thermal test chip with a microchannel cooler bonded to it packaged in a single chip module was also demonstrated for a chip power density greater than 300W/cm2. Coolers of this design should be able to cool chips with average power densities of 400W/cm2 or more

An advanced multichip module (MCM) for high-performance UNIX servers

In 2001, IBM delivered to the marketplace a high-performance UNIX?®-class eServer based on a four-chip multichip module (MCM) code named Regatta. This MCM supports four POWER4 chips, each with 170 million transistors, which utilize the IBM advanced copper back-end interconnect technology. Each chip is attached to the MCM through 7018 flip-chip solder connections. The MCM, fabricated using the IBM high-performance glass-ceramic technology, features 1.7 million internal copper vias and high-density top-surface contact pad arrays with 100-?µm pads on 200-?µm centers. Interconnections between chips on the MCM and interconnections to the board for power distribution and MCM-to-MCM communication are provided by 190 meters of co-sintered copper wiring. Additionally, the 5100 off-module connections on the bottom side of the MCM are fabricated at a 1-mm pitch and connected to the board through the use of a novel land grid array technology, thus enabling a compact 85-mm ?? 85-mm module footprint that enables 8- to 32-way systems with processors operating at 1.1 GHz or 1.3 GHz. The MCM also incorporates advanced thermal solutions that enable 156 W of cooling per chip. This paper presents a detailed overview of the fabrication, assembly, testing, and reliability qualification of this advanced MCM technology.

High Performance and Sub-Ambient Silicon Microchannel Cooling

High performance single-phase Si microchannel coolers have been designed and characterized in single chip modules in a laboratory environment using either water at 22°C or a fluorinated fluid at temperatures between 20 and −40°C as the coolant. Compared to our previous work, key performance improvements were achieved through reduced channel pitch (from 75 to 60 microns), thinned channel bases (from 425 to 200 microns of Si), improved thermal interface materials, and a thinned thermal test chip (from 725 to 400 microns of Si). With multiple heat exchanger zones and 60 micron pitch microchannels with a water flow rate of 1.25 lpm, an average unit thermal resistance of 15.9 C-mm2 /W between the chip surface and the inlet cooling water was demonstrated for a Si microchannel cooler attached to a chip with Ag epoxy. Replacing the Ag epoxy layer with an In solder layer reduced the unit thermal resistance to 12.0 C-mm2 /W. Using a fluorinated fluid with an inlet temperature of −30°C and 60 micron pitch microchannels with an Ag epoxy thermal interface layer, the average unit thermal resistance was 25.6 C-mm2 /W. This fell to 22.6 C-mm2 /W with an In thermal interface layer. Cooling >500 W/cm2 was demonstrated with water. Using a fluorinated fluid with an inlet temperature of −30°C, a chip with a power density of 270 W/cm2 was cooled to an average chip surface temperature of 35°C. Results using both water and a fluorinated fluid are presented for a range of Si microchannel designs with a channel pitch from 60 to 100 microns.Copyright

Thermal and mechanical analysis and design of the IBM Power 775 water cooled supercomputing central electronics complex

Back in 2008 IBM reintroduced water cooling technology into its high performance computing platform, the Power 575 Supercomputing node/system. Water cooled cold plates were used to cool the processor modules which represented about half of the total system (rack) heat load. An air-to-liquid heat exchanger was also mounted in the rear door of the rack to remove a significant fraction of the other half of the rack heat load; the heat load to air. Water cooling enabled a compute node with 34% greater performance (Flops), resulted in a processor temperature 20-30°C lower than that typically provided with air cooling, and reduced the power consumed in the data center to transfer the IT heat to the outside ambient by as much as 45%. The next generation of this platform, the Power 775 Supercomputing node/system, is a significant leap forward in computing performance and energy efficiency. The compute node and system were designed from the start with water cooling in mind. The result, a system with greater than 95% of its heat load conducted directly to water; a system that, together with a rear door heat exchanger, removes 100% of its heat load to water with no requirement for room air conditioning. In addition to the processor, memory, power conversion, and I/O electronics conduct their heat to water. Included within the framework of the system is a disk storage unit (disc enclosure) containing an inter-board air-to-water heat exchanger. This paper will detail key thermal and mechanical design issues associated with the Power 775 server drawer or central electronics complex (CEC). Topics to be addressed include processor and optical I/O Hub Module thermal design (including thermal interfaces); water cooled memory design; module cold plate designs; CEC level water distribution; module level structural analyses for thermal performance; module/board land grid array (LGA) load distribution; effect of load distribution on module thermal interfaces; and the effect of cold plate tubing on module (LGA) loading.

Development of a 50mm dual Flip Chip Plastic Land Grid Array package for server applications

For many years, the Flip Chip Plastic Ball Grid Array (FC-PBGA) has been the preferred packaging solution for microprocessors and high performance ASICs. IBM has developed a dual chip Flip Chip Plastic Land Grid Array (FC- PLGA) package to support low and mid range server solutions. This organic 50 mm times 50 mm lead reduced package solution uses a 6-4-6 build-up laminate with two large chips consisting of a processor (22 times 16 mm) and a memory cache (15 times 13 mm) in a single piece lid capping solution. In this paper, we will summarize development activities performed in order to achieve a reliable product while dissipating up to 200 Watts mostly from the microprocessor chip. One of the many key issues to overcome was the assurance of good package thermal stability with such large silicon area coverage over the flexible organic chip carrier. Special chip and module test vehicles were designed and fabricated in order to evaluate the mechanical, electrical, and thermal behaviour of the package post assembly and throughout stress testing. The assembly process development activities performed to support the desired application will be discussed in conjunction with mechanical modeling results. In addition, thermal data will be presented showing the positive results obtained as well as good correlation to the thermal and mechanical models.

Manufacturing Considerations and Tools for Flip Chip Assembly

The complexity of building an area-array manufacturing line is similar to constructing standard electronic-packaging facilities. Decisions which affect the productivity of a manufacturing plant span from initial package design to finished product inspection. As with any manufacturing operation, tradeoffs must be constantly evaluated to achieve an acceptable balance between quality, production, cost and reliability objectives.