Kenny L. Doan

Magnetic field optimization in a dielectric magnetically enhanced reactive ion etch reactor to produce an instantaneously uniform plasma

The effect of magnetic field on plasma uniformity was investigated for a capacitively coupled plasma in a dielectric etch chamber and a tool to measure the dc bias uniformity across the high-powered cathode (e.g., 1200 W) was developed. At that power, the dc bias can be as high as 1500 V at 50 mT. A 5% variation in the dc bias across the cathode corresponds to a 75 V potential drop across the wafer, which may in turn cause degradation or breakdown of gate oxide structures. Therefore control of the instantaneous plasma uniformity is important to minimize device damage. The primary effect of the magnetic field on instantaneous plasma uniformity is through the E×B drift force which, because of the strong electric field at the cathode surface at high powers, dominates the other magnetic field effects on the plasma. dc bias measurements show that the plasma nonuniformity can be optimized by adjusting the gradient of the magnetic field, and thus the E×B drift force, across the cathode over a wide range of magne...

Understanding the evolution of trench profiles in the via-first dual damascene integration scheme

The introduction of copper interconnects into integrated circuits has increased the use of dual damascene dielectric etch applications because copper films are difficult to plasma etch. Fencing and faceting around the via hole during the trench etch of the via-first dual damascene integration scheme are particularly detrimental and can lead to problems during copper metallization and ultimately to device failure. Therefore, it is imperative that the evolution of these features be understood so that they can be avoided. In this article we will begin with an overview of the via-first dual damascene integration scheme. Experimental results will then be presented that indicate the evolution of these features is heavily dependent upon the existing via profile and whether bottom antireflection coating and/or photoresist is in the via hole prior to starting the trench etch. An empirical model for fence formation was then confirmed by a simple profile simulator written in Visual Basic. Finally, several options fo...

Plasma charging damage characterization of 200mm and 300mm dielectric etch chambers using bias voltage diagnostic cathodes

A V/sub DC/ bias diagnostic cathode is developed to measure the plasma-induced self bias uniformity on the wafer and the correlation to device charging damage on both 200mm and 300mm dielectric etch chambers. Multiple probe pins are buried within the ceramic electrostatic chuck surface with only the top surface tips exposed to plasma. The wafer surface DC bias voltage during the plasma process can be directly measured in-situ from these probes with built-in circuitry. The maximum bias difference (/spl Delta/V/sub DC/ = V/sub DC(max)/ - V/sub DC(min)/) of measured on-wafer V/sub DC/ correlates to device damage during the plasma process. Comparing 200mm and 300mm chamber measurement results, the scale-up process in 300mm chamber is identified to have similar uniformity performance as in 200mm chamber. Using device calibration data compared to /spl Delta/V/sub DC/ values, the plasma damage performance in both 200mm and 300mm chambers can be predicted in early chamber or process development stages.