Keh-Jeng Chang

Use of short-loop electrical measurements for yield improvement

Modern submicron processes are more sensitive to both random and systematic wafer-level process variation than ever before. Given the dimensional control limitations of new technologies, the amount of wafer-to-wafer and within wafer nonuniformity of many steps is becoming a significant fraction of the total error budget, which already includes the usual step-to-step allocations. However, a significant portion of the total observed variability is systematic in nature. Accordingly, particle defects may not continue to dominate parametric yield loss without improved understanding of parametric variations. In this paper, we demonstrate the use of short-loop electrical metrology to carefully characterize and decouple wafer-level variability of several critical processing steps. More specifically, we present our method and give results obtained from variability analyses for lithography critical dimension (CD) and inter-level dielectric (ILD) thickness control. Using statistically designed experiments and dedicated test structures, the main factors affecting dielectric thickness variability has been identified. The systematic variability from a wafer stepper has been extracted using a physically based statistical data filter. Once isolated, the deterministic variability can be modeled and controlled to enhance process and circuit design for manufacturability (DFM). We hope that in the future this work will be coupled with novel DFM-oriented CAD tools that encapsulate this information in a fashion that makes it useful to process and circuit designers. >

2001 needs for multi-level interconnect technology

Looks at the materials and thermal alternatives for scaled, next-century VLSI/ULSI interconnects. It is shown that ad hoc executions of programs to calculate interconnect parameters for VLSI/ULSI design and analysis are too time-consuming to be practical. The tool used in this study to model a hypothetical interconnect system was Hewlett Packards HTVE (HP Interconnect Value Extractor). >

Parameterized SPICE subcircuits for multilevel interconnect modeling and simulation

The authors describe a parameterized interconnect model library generator that provides VLSI designers with a direct link between numerical method-based capacitance simulators and SPICE-like circuit simulators. As a result, interconnect parasitics are parameterized in a manner similar to the parameterization of transistors in SPICE. Therefore, the effort and time needed by circuit designers or EDA tools to prepare distributed multiline R, C SPICE decks for circuit simulations is drastically reduced. >

HIVE: an efficient interconnect capacitance extractor to support submicron multilevel interconnect designs

A novel paradigm for efficiently providing 2-D and 3-D submicron multilevel (SMML) interconnect capacitances to support VLSI/ULSI designs regarding RC delay, electromigration, and crosstalk has been developed. According to SMML interconnect process measurements and simulations, when the interconnect width/space changes, the corresponding changes of the ground and coupling capacitances are linear in some cases and nonlinear in other cases. A set of representative SMML layout structures is selected so that rigorous 2-D and 3-D simulations are done for the nonlinear changes in advance, and fast interpolations/extrapolations are done for the linear changes when circuit designers specify the width/space of interconnects.<<ETX>>

Statistical metrology for interlevel dielectric thickness variation

Statistical metrology seeks to assess the sources and magnitude of variation in semiconductor manufacturing. The methodology emphasizes electrical measurements resulting from short process flows, statistical design of experiments and analysis of data, and close coupling to technology computer aided design tools for the interpretation of data. In this paper, we apply statistical metrology to interlevel dielectric thickness variation. Capacitive test structures, in conjunction with resistive line width structures and two-dimensional capacitance simulations, are used to estimate ILD thickness for a variety of layout and process factors in a poly-metal BPSG planarization process. The methodology is successful in highlighting the key factors, including underlying structure line width spacing,and finger length that impact ILD thickness. Future work will examine other planarization processes, including chemical mechanical polishing.

Interconnect modeling and design in high-speed VLSI/ULSI systems

A batch-oriented interconnect modeling system, IPDA (Interconnect Performance Design Assistant), developed for interconnect modeling and design in high-speed VLSI/ULSI systems, is presented. Intrachip communication is degraded by RC delay and crosstalk, and electromigration generates a serious reliability problem. Several approaches for alleviating these problems are quantitatively analyzed, and optimum approaches are recommended. In the interchip communication, reflection, crosstalk, and simultaneous switching noise, degrade the system performance. Approaches for solving these problems are introduced and analyzed for practical applications.<<ETX>>

IPDA: interconnect performance design assistant

IPDA is a generic interconnect performance design assistant that integrates a finite-difference numerical simulation method, linear interpolation algorithm, interactive performance synthesis methodology, and lossless/lossy transmission-line SPICE modeling capability into a spreadsheet-style graphical user interface. The algorithm, implementation, and methodology of IPDA are described and an application example is discussed. Although the authors describe electrical performance measures for given geometry and material parameters of conductors and dielectrics, IPDA can be customized for other packaging measures such as reliability and thermal and cost effects through spreadsheet interface and calculations. IPDA assists users in selecting interconnect technologies for design-for-performance goals and also in optimizing interconnect performance designs for the full hierarchy of packaging including IC/multichip module/printed circuit board/lead-bonding/via interconnect designs.<<ETX>>

Nondestructive Multilevel Interconnect Parameter Characterization For High-performance Manufacturable VLSI Technologies

One of the challenges in VLSI fabrication is to design submicron multilevel metals with high yield. This paper describes a concurrent engineering methodology that provides semiconductor engineers and VLSI circuit designers with an efficient test, modeling, and SPICE-level simulation environment. At the beginning of interconnect technology selection/evaluation, comprehensive and representative 3-D interconnect test structures are designed and fabricated for each technology option. The geometric parameters and their standard deviations are then characterized by measured data using 3-D-simulated ‘thickness vs. capacitance’ curves. A spreadsheet-based Universal Multilevel Interconnect Model Evaluator reads the characterized geometric parameters and generates maximum-, nominal-, and minimum-case parameterized interconnect SPICE subcircuits for each technology to model global and critical VLSI interconnect networks, such as clock trees, power distribution, control/data buses, and word/bit lines. In this way, new interconnect options can be evaluated using rigorous SPICE simulations.

Parameterized SPICE subcircuits for submicron multilevel interconnect modeling

A parameterized interconnect modeling system which provides VLSI designers with a direct link between finite-difference 2-D/3-D capacitance simulators and SPICE simulators is described. In this way, both the device modeling and the interconnect modeling are parameterized, and the time needed to generate SPICE inputs is estimated to decrease by two or three orders of magnitude with this approach.<<ETX>>

Physical and technological limitations and their optimization in submicron ULSI interconnect

The trend of the performance degradation, noise and reliability issues and their potential solutions are analyzed for submicron ULSI interconnect lines. The analysis shows that a copper (Cu) line will improve electromigration, but not the interconnect delay and cross-talk noise significantly. The low temperature operation improves the interconnect delay and electromigration, but increases the cost of system packaging. The optimum approach a combination of additional layers of nonscaled metal lines in a higher level and the use of repeaters to maximize the performance, noise and reliability and to minimize the risk and cost.<<ETX>>