N. Hamatake

A 300-MHz 16-b BiCMOS video signal processor

A 300-MHz 16-b full-programmable parallel-pipelined video signal processor ULSI has been developed. With multifunctional arithmetic units to achieve parallel vector processing, and with a phase-locked-loop (PLL) type clock generator to help attain the 300-MHz internal operating speed, this ULSI is able to attain, with only one chip, 30-frame-per-second full-CIF video data coding based on CCITT H.261. Two different types of pass-transistor BinMOS circuits have been developed to help achieve an access time of 3 ns for a 146-kb SRAM and for data buses. Fabricated with a 0.5- mu m BiCMOS and triple-layer metallization process technology, the video signal processor ULSI contains 1.27-million transistors in a 16.5*17.0-mm/sup 2/ die area. >

A programmable clock generator with 50 to 350 MHz lock range for video signal processors

Using 0.5-/spl mu/m CMOS triple-layer Al technology, a programmable clock generator based on a PLL (phase-locked loop) circuit has been developed for use as an on-chip clock generator in a 300-MHz video signal processor. It generates an internal clock whose frequency is an integral multiple of an external clock frequency, and its oscillating frequency ranges from 50 to 350 MHz. Experimental results show that the clock generator generates a 297-MHz clock with jitter reduced to 180 ps with a 27-MHz input clock, and that it oscillates at up to 348 MHz with a 31.7-MHz input clock.

A 2.4-ns, 16-bit, 0.5-/spl mu/m CMOS arithmetic logic unit for microprogrammable video signal processor LSIs

A 16-b arithmetic logic unit (ALU) has been developed for achieving high-speed microprogrammable video signal processor LSIs. The ALU employs a parallel architecture with newly developed high-speed circuit operations, including highly parallel addition, operand look-ahead overflow detection, and carry select zero-flag detection. The unit contains 6,272 transistors in a 1.50 mm /spl times/ 1.09 mm die area using 0.5-/spl mu/m CMOS process technology, and 2.4-ns ALU operations have been successfully achieved.

Comparison of fully depleted and partially depleted mode transistors for practical high-speed, low-power 0.35 /spl mu/m CMOS/SIMOX circuits

Although attractive features of fully depleted mode transistors have already been clarified, essential roles of the fully depleted mode itself in improved performance of digital circuits have not been shown clearly. In this study, we examined such parameters as the propagation delay time and power consumption of 0.35-/spl mu/m CMOS/SIMOX gates (inverter, 2-6NAND, 2-6NOR) composed of fully depleted (FD), near fully depleted (n-FD), or partially depleted (PD) mode transistors with no body-contacts, and discussed the essentially important factors for high performances of CMOS/SIMOX circuits.

A 300-MHz, 16-bit, 0.5-/spl mu/m BiCMOS digital signal processor core LSI

A 300-MHz, 16-bit, 0.5-/spl mu/m BiCMOS digital signal processor (DSP) core LSI, which employs a parallel processing architecture, 300-MHz redundant binary arithmetic units, and a sophisticated high-performance electrical design, has been developed for video signal processing. Measured clock skew and critical path delay are less than 80 ps and 2.6 ns, respectively. It has a parallel processing architecture capable of discrete cosine transform (DCT) operations for efficient motion picture coding in video signal processing.

High-speed performance of 0.35 μm CMOS gates fabricated on low-dose SIMOX substrates with/without an N-well underneath the buried oxide layer

We present experimental results concerning the propagation delay time of the 0.35 /spl mu/m CMOS gate chains (inverter, 3NAND, and 3NOR) fabricated on low-dose SIMOX substrates with and without the N-well formed underneath the buried oxide layer in the PMOS region. Using such experimental data as the capacitance voltage characteristics of the buried oxide layer, and the enhanced PMOS transistor drivability due to the negative back bias effect, we clarify the most essential factor of the high-speed performance of the CMOS/SIMOX circuits fabricated on a low-dose SIMOX substrate.

Possible causes of trace metallic contaminants in SIMOX and BESOI substrates

From reliability point of view, detailed studies on metallic contaminants in SIMOX and BESOI substrates are strongly required. However, a main cause of metallic contaminants in SIMOX or BESOI substrates has not been clarified yet. In this paper, we present our VPD-AAS chemical analysis data on an extremely small quantity of metallic elements (below the detection limits of SIMS) detected in various SIMOX (Tsoi=100-320 nm) and BESOI (Tsoi=1.5 /spl mu/m) substrates, and discuss possible causes of these trace metallic contaminants. These are concluded to be down to the wafer cleaning process and annealing.

The most essential factor for high-speed, low-power 0.35 μm complementary metal-oxide-semiconductor circuits fabricated on separation-by-implanted-oxygen (SIMOX) substrates

We present experimental data concerning the propagation delay time and the power consumption of 0.35 µ m complementary metal-oxide-semiconductor (CMOS) gates (inverter, NAND, NOR) fabricated on the commercial standard high dose separation-by-implanted-oxygen (SIMOX) substrates. Each CMOS gate was composed of the fully depleted (FD) mode N- and P-type metal-oxide-semiconductor (NMOS and PMOS) transistors or the partially depleted (PD) mode ones with no body-contact. On the basis of the experimental data, together with SPICE simulation results, we show that the FD-mode is not the primary factor for high-speed, low-power performances of the CMOS/SIMOX circuits, but the reduced drain parasitic capacitance (both the bottom and the peripheral components) with the thin film silicon-on-insulator (SOI) structure is. Furthermore, we show the significance of the design and control of the transistor threshold voltage and/or the off-state leakage current for high-speed, low-power CMOS/SIMOX circuits.

High speed performance of 0.35 /spl mu/m CMOS gates fabricated on low dose SIMOX substrates with/without N-well underneath the buried oxide layer

High speed performances of CMOS/SIMOX circuits have been demonstrated using the low dose SIMOX substrate in spite of the thin (80nm) buried oxide layer. The following two factors have been pointed out to understand the results: (i) the depletion layer which spreads underneath the buried oxide (BOX) layer, and (ii) the Vth-lowering in the PMOS transistor due to the negative back bias (VGB=-VDD) effect. However, the correlations between the high speed performance and these two factors have not been shown in detail. In this paper, we clarify the nature of the high speed performance of the fully depleted mode ultrathin CMOS/SIMOX gates fabricated on the low dose SIMOX substrate on the basis of our experimental results.