Kouichi Kumagai

A novel powering-down scheme for low Vt CMOS circuits

In this paper, a novel powering-down scheme with a virtual power/ground rails clamp (VRC) circuit is proposed. It features the 98% off-leakage current reduction, without the operating speed degradation and the high Vt transistors. The VRC scheme does not need the extra circuits and the timing design for data holding in the sleep mode. This effectiveness has been confirmed by the 24-bit multiplier-accumulator, using 0.25 /spl mu/m CMOS double-layer metal technology.

System-in-silicon architecture and its application to H.264/AVC motion estimation for 1080HDTV

System-in-silicon (SiS) is a multi-chip architecture to realize wide bandwidth communication between logic and memory with low power. The application of SiS to H.264/AVC motion estimation is presented. DRAM is integrated with 23.1 Gb/s bandwidth and 1.6pJ/b data transfer efficiency, realizing real-time 1080HDTV processing with 263.1GB/s. The authors present a system-in-silicon architecture with 1024b inter-chip bus to provide high-bandwidth low-power connectivity between logic and memory. The highly parallel architecture also allows low frequency (25MHz) operation while achieving real-time motion estimation for 1080HDTV. The solution achieves the required 23.1 Gb/s bandwidth and associated processing for motion estimation at a power level of 190mW

A 300-MHz 16-b BiCMOS video signal processor

A 300-MHz 16-b full-programmable parallel-pipelined video signal processor ULSI has been developed. With multifunctional arithmetic units to achieve parallel vector processing, and with a phase-locked-loop (PLL) type clock generator to help attain the 300-MHz internal operating speed, this ULSI is able to attain, with only one chip, 30-frame-per-second full-CIF video data coding based on CCITT H.261. Two different types of pass-transistor BinMOS circuits have been developed to help achieve an access time of 3 ns for a 146-kb SRAM and for data buses. Fabricated with a 0.5- mu m BiCMOS and triple-layer metallization process technology, the video signal processor ULSI contains 1.27-million transistors in a 16.5*17.0-mm/sup 2/ die area. >

A programmable clock generator with 50 to 350 MHz lock range for video signal processors

Using 0.5-/spl mu/m CMOS triple-layer Al technology, a programmable clock generator based on a PLL (phase-locked loop) circuit has been developed for use as an on-chip clock generator in a 300-MHz video signal processor. It generates an internal clock whose frequency is an integral multiple of an external clock frequency, and its oscillating frequency ranges from 50 to 350 MHz. Experimental results show that the clock generator generates a 297-MHz clock with jitter reduced to 180 ps with a 27-MHz input clock, and that it oscillates at up to 348 MHz with a 31.7-MHz input clock.

A 2.4-ns, 16-bit, 0.5-/spl mu/m CMOS arithmetic logic unit for microprogrammable video signal processor LSIs

A 16-b arithmetic logic unit (ALU) has been developed for achieving high-speed microprogrammable video signal processor LSIs. The ALU employs a parallel architecture with newly developed high-speed circuit operations, including highly parallel addition, operand look-ahead overflow detection, and carry select zero-flag detection. The unit contains 6,272 transistors in a 1.50 mm /spl times/ 1.09 mm die area using 0.5-/spl mu/m CMOS process technology, and 2.4-ns ALU operations have been successfully achieved.

A new SRAM cell design using 0.35 /spl mu/m CMOS/SIMOX technology

In SOI/CMOS devices, it is known that the integration density and the circuit performance can be improved using a layout of abutted n/sup +/ and p/sup +/ drain regions. Utilizing these advantages in the SOI technology, we have designed a new 6-T memory cell and have developed a 128 Kb synchronous SRAM macro (SOI-SRAM) by 0.35 /spl mu/m CMOS/SIMOX technology. The SOI-SRAM performance is compared with the reference SRAM macro (REF-SRAM) which is designed with the bulk CMOS memory cell layout.

Comparison of fully depleted and partially depleted mode transistors for practical high-speed, low-power 0.35 /spl mu/m CMOS/SIMOX circuits

Although attractive features of fully depleted mode transistors have already been clarified, essential roles of the fully depleted mode itself in improved performance of digital circuits have not been shown clearly. In this study, we examined such parameters as the propagation delay time and power consumption of 0.35-/spl mu/m CMOS/SIMOX gates (inverter, 2-6NAND, 2-6NOR) composed of fully depleted (FD), near fully depleted (n-FD), or partially depleted (PD) mode transistors with no body-contacts, and discussed the essentially important factors for high performances of CMOS/SIMOX circuits.

A 3D analysis of source/drain capacitance in SOI MOSFET for practical circuit design

It is well known that the small capacitance of the source/drain (S/D) region in MOS/SOI devices is one of the most attractive characteristics for the circuit performance improvements. In order to perform the implementation of the three-dimensional (3D) effects of the S/D capacitance into circuit simulators for more precise simulations, it is strongly required to estimate 3D dependence of the S/D capacitance on transistor layout patterns. However, such effects of the 3D coupling between the adjacent S/D regions have not been investigated in detail. In this study, we analyzed 3D effects of the S/D capacitance in MOS/SOI devices using in-house simulators, and discussed the contribution of the 3D effects on the total S/D capacitance.

Design methodology for low power, high-speed CMOS devices utilizing SOI technology

We have compared CMOS gate performances between bulk and SOI structures, using the circuit simulator SPICE with the simplest assumptions. Main results are as follows: (1) We have demonstrated that it is possible to estimate CMOS/SOI performances using the circuit simulator SPICE without any specific physical models for SOI transistors. (2) The reduction effect of the drain parasitic capacitance by the CMOS/SOI technology becomes more remarkable with a decrease in the supply voltage. (3) Just by increasing the channel width of the CMOS/SOI keeping its power consumption equal to that of the CMOS/BULK, the propagation delay time dependence on large load capacitance can be improved dramatically with higher drivability.<<ETX>>

A 300-MHz, 16-bit, 0.5-/spl mu/m BiCMOS digital signal processor core LSI

A 300-MHz, 16-bit, 0.5-/spl mu/m BiCMOS digital signal processor (DSP) core LSI, which employs a parallel processing architecture, 300-MHz redundant binary arithmetic units, and a sophisticated high-performance electrical design, has been developed for video signal processing. Measured clock skew and critical path delay are less than 80 ps and 2.6 ns, respectively. It has a parallel processing architecture capable of discrete cosine transform (DCT) operations for efficient motion picture coding in video signal processing.