Koji Murano

Capability of etched multilayer EUV mask fabrication

Recently, development of next generation extremely ultraviolet lithography (EUVL) equipment with high-NA (Numerical Aperture) optics for less than hp10nm node is accelerated. Increasing magnification of projection optics or mask size using conventional mask structure has been studied, but these methods make lithography cost high because of low through put and preparing new large mask infrastructures. To avoid these issues, etched multilayer EUV mask has been proposed. As a result of improvement of binary etched multilayer mask process, hp40nm line and space pattern on mask (hp10nm on wafer using 4x optics) has been demonstrated. However, mask patterns are easily collapsed by wet cleaning process due to their low durability caused by high aspect ratio. We propose reducing the number of multilayer pairs from 40 to 20 in order to increase durability against multilayer pattern collapse. With 20pair multilayer blank, durable minimum feature size of isolated line is extended from 80nm to 56nm. CD uniformity and linearity of 20pair etched multilayer pattern are catching up EUV mask requirement of 2014.

Patterning of EUVL binary etched multilayer mask

Recently, development of next generation extremely ultraviolet lithography (EUVL) equipment with high-NA (Numerical Aperture) optics for less than hp10nm node is accelerated. While studying more than 0.45 NA, incident angle distribution of EUV light irradiation to mask becomes larger. It induces degradation of exposure margin to form horizontal line pattern (perpendicular to EUV light direction) because of large mask 3D effect. In order to resolve this issue, we evaluate binary etched multilayer mask structure, unlike conventional stacked absorber structure. As a result of improvement of binary etched multilayer mask process, hp40nm line and space pattern on mask (hp10nm on wafer using 4X optics) is demonstrated. This result suggests the capability of high-NA EUVL with 6inch and 4X optics with new mask structure.

Improvement of EUVL mask structure with black border of etched multilayer

For EUVL mask with thinner absorber, it is necessary to make black border area in order to suppress the leakage of the EUV light from the adjacent exposure shots Black border of etched multilayer is promising structure in terms of light-shield capability and mask process simplicity. However, EUVL masks with this structure do not have electrical conductivity between the inside and the outside of black border. Inspection area including device patterns belongs to the inside of the black border. In case that quality check for EUVL masks is performed with E-beam inspection, the area is floating. As a result, electrification to mask pattern occurs and causes degradation of E-beam inspection accuracy when the mask is inspected by E-beam inspection tool. In this paper, we refine EUVL mask structure with black border of etched multilayer in order to improve electrical conductivity. We will show evaluation results of E-beam inspection accuracy, and discuss specifications of electrically conductive black border area.

Process liability evaluation for beyond 22nm node using EUVL

Extreme ultraviolet lithography (EUVL) is the most promising candidate for the manufacture of devices with a half pitch of 32 nm and beyond. We are now evaluating the process liability of EUVL in view of the current status of lithography technology development. In a previous study, we demonstrated the feasibility of manufacturing 32-nm-node devices by means of a wafer process that employed the EUV1, a full-field step-and-scan exposure tool. To evaluate yield, a test pattern was drawn on a multilayer resist and exposed. After development, the pattern was replicated in SiO2 film by etching, and metal wires were formed by a damascene process. Resolution enhancement is needed to advance to the 22- nm node and beyond, and a practical solution is off-axis illumination (OAI). This paper presents the results of a study on yield improvement that used a 32-nm-node test chip, and also clarifies a critical issue in the use of EUVL in a wafer process for device manufacture at the 22-nm node and beyond.

Process liability evaluation for EUVL

This paper concerns the readiness of extreme ultraviolet lithography (EUVL) for high-volume manufacture based on accelerated development in critical areas and the construction of a process liability (PL) test site that integrates results in these areas. The overall lithography performance was determined from the performance of the exposure tool, the printability obtainable with the resist, mask fabrication with accurate critical dimension (CD) control, and correction technology for mask data preparation. The EUV1 exposure tool can carry out exposure over the full field (26 mm × 33 mm) at a resolution high enough for 32-nm line-and-space patterns when Selete Standard Resist 3 (SSR3) is used. Thus, the test site was designed for the full-field exposure of various pattern sizes [half-pitch (hp) 32-50 nm]. The CD variation of the mask was found to be as good as 2.8 nm (3σ); and only one printable defect was detected. The effect of flare on CD variation is a critical issue in EUVL; so flare was compensated for based on the point spread function for the projection optics of the EUV1 and aerial simulations that took resist blur into account. The accuracy obtained when an electronic design automation (EDA) tool was used for mask resizing was found to be very good (error ≤ ±2 nm). Metal wiring patterns with a size of hp 32 nm were successfully formed by wafer processing. The production readiness of EUVL based on the integration of results in these areas was evaluated by electrical tests on low-resistance tungsten wiring. The yield for the electrically open test for hp 50 nm (32-nm logic node) and hp 40 nm (22-nm logic node) were found to be over 60% and around 50%, respectively; and the yield tended to decrease as patterns became smaller. We found the PL test site to be very useful for determining where further improvements need to be made and for evaluating the production readiness of EUVL.

Process liability evaluation for extreme ultraviolet lithography

This work concerns the readiness of extreme ultraviolet lithography (EUVL) for high-volume manufacturing based on accelerated development in critical areas, and the construction of a process liability (PL) test site that integrates results in these areas. Overall lithography performance is determined from the performance of the exposure tool, the printability obtainable with the resist, mask fabrication with accurate critical dimension (CD) control, and correction technology for mask data preparation. The EUV1 exposure tool can carry out exposure over the full field (26 × 33 mm) at a resolution high enough for 32-nm line-and-space patterns when Selete Standard Resist 3 (SSR3) is used. The effect of flare on CD variation is a critical issue in EUVL, so flare is compensated for based on the point spread function for the projection optics of the EUV1 and aerial simulations that take resist blur into account. Production readiness of EUVL based on the integration of results in these areas is evaluated by electrical tests on low-resistance tungsten wiring. We find the PL test site to be very useful for determining where further improvements need to be made and for evaluating the production readiness of EUVL.

Defect management of EUV mask

Extreme Ultraviolet Lithography (EUVL) is a promising technology for the fabrication of ULSI devices with 20nm half-pitch node. One of the key challenges before EUVL is to achieve defect-free masks. There are three main categories of mask defects: multilayer defects which cause phase defects, absorber pattern defects, and particles during blank/mask fabrication or mask handling after mask fabrication. It is important to manage multilayer defect because small multilayer defects are difficult to be identified by SEM/AFM after mask patterning and can impact wafer printing. In this paper, we assess blank defect position error detected by 3rd generation blank inspection tool, using blank defect information from blank supplier and 199nm wavelength patterned mask inspection tool NPI-7000. And we rank blank defect in the order of projection defect size to multilayer in order to estimate blank defect printability. This method avoids overestimating the number of potential killer defects that hardly be identified by SEM/AFM under the condition that EUV-AIMS is not available.

High performance photomask technology with the advanced binary film

A new photomask technology with the Advanced Binary Film (ABF) by HOYA has been established. The film of relatively low thickness is expected to show the best lithography performance. The simple film structure of thin film of chemically amplified resist, as a mask layer for etching, on the thin ABF film enables us to obtain sub-50nm small features in a photomask. The thinness of the film also helps to avoid pattern collapse in cleaning steps. The photomask with ABF expecting the best currently available lithography performance shows the best achievable durability for use in ArF lithography process steps and the best attainable feasibility in the fabrication process steps for leading edge photomasks.

Study of CD variation at EUV mask fabrication occurred by electric conduction from top to back side

Extreme Ultra Violet Lithography (EUVL) is the most leading next generation lithographic technology post ArF immersion lithography. The Structure of EUV mask differ from traditional photomask., especially backside coating. E-chuck is employed to fix the EUV mask on the scanner. Therefore a conductive film on backside of the EUV mask blank is needed. We investigated what have an influence on mask manufacturing process caused by the backside coating differed from a traditional photomask. From our experiment, at the mask fabrication process, especially RIE process to etch Ta absorber, the CD variation is occurred by electric conduction between the backside conductive coating and the absorber on the Mo/Si multi-layer. As a result, the EUV mask blank without electric conduction between the backside conductive coating and the absorber on the Mo/Si multilayer is necessary.

More evolved PGSD (proximity gap suction developer) for controlling movement of dissolution products

PGSD is one of the solutions as a developer of 70 nm node generation mask fabrication. To make 55 nm node generation mask, CD error induced by loading effect (loading-effect-induced CD error) must be reduced. As is generally known, primary cause of loading effect is dissolution products that hinder the progress of development. We think that it is the key in development technology to control movement of dissolution products and to disperse dissolution products uniformly for minimizing the loading-effect-induced CD error. In this paper, we propose a new concept and procedure to optimize the movement direction and the amount of dissolution products.