Koji Yamakawa

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes

An 87.7 mm2 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic capacitance sensing scheme, and dual metal plateline scheme - reduce bitline capacitance from 100 fF to 60 fF. As a result, a cell signal of ±220 mV is achieved even with the small cell size of 0.252 ¿m2. An 800 Mb/s/pin read/write bandwidth at 400 MHz clock is realized by installing SDRAM compatible DDR2 interface, and performance is verified by simulation. The internal power-line bounce noise due to 400 MHz clock operation is suppressed to less than 50 mV by an event-driven current driver, which supplies several hundreds of mA of current within 2 ns response. The precise timing and voltage controls are achieved by using the data stored in a compact FeRAM-fuse, which consists of extra FeRAM memory cells placed in edge of normal array instead of conventional laser fuse links. This configuration minimizes area penalty to 0.2% without cell signal degradation.

Solder bumper formation using electroless plating and ultrasonic soldering

Aluminum electrodes in the Si wafer were surface-treated in the sequence palladium activation, Ni-P electroless plating, ultrasonic soldering with Pb-1Sn solder, and dipping in Sn-37Pb to form second-stage solder bumps. The average bump height and the shear force were 20.3 mu m and 26.8 g/pad, respectively. The shear force did not decrease after the heating test (150 degrees C*1000 h) or thermal cycle test (-65 degrees C (--) room temperature (--) 150 degrees C, 300 cycles). Aluminum diffused to amorphous Ni-P through the Pd layer, Ni-Sn intermetallic compounds were formed at the Pb-1 Sn/Ni-P interface. The low-cost polyester tape-automated bonding was utilized to melt low temperature second solder on inner lead bonding. No bridge occurred when applying this technique to an LSI device with 376 electrodes, 100 mu m wide with 150 mu m pitch.<<ETX>>

A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode

A 64Mb chain FeRAM implemented in 0.13mum 3M CMOS technology is described. A quad-BL architecture reduces the die area by 6.5% and realizes 87.5mm2 die with an effective cell-size of 0.7191mum2 while eliminating BL-BL coupling noise. A high-speed ECC circuit and cell data write-back scheme achieves read/write cycle time of 60ns and 200MB/S burst

A 32-Mb chain FeRAM with segment/stitch array architecture

A 96mm/sup 2/, 32Mb chain FeRAM in 0.20/spl mu/m 3M CMOS and stacked capacitor technology is described. Cell efficiency of 65.6% is realized by compact memory cell structure and segment/stitch WL architecture. The word line power-on/off sequence protects the data from startup noise. A 3/spl mu/A standby current bias generator and compatible access mode SRAM are implemented for mobile applications.

A 76 mm/sup 2/ 8 Mb chain ferroelectric memory

An 8 Mb chain FeRAM uses 0.25 /spl mu/m 2-metal CMOS technology. A one-pitch-shift cell realizes 5.2 /spl mu/m/sup 2/ cell area. A chain architecture with a hierarchical wordline scheme gives 76 mm/sup 2/ die. Random access time is 40 ns, and cycle time is 70 ns at 3.0 V.

A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode

A 64-Mb chain ferroelectric RAM (chainFeRAM) is fabricated using 130-nm 3-metal CMOS technology. A newly developed quad bitline architecture, which combines folded bitline configuration with shield bitline scheme, eliminates bitline-bitline (BL-BL) coupling noise. The quad bitline architecture also reduces the number of sense amplifiers and activated bitlines, resulting in the reduction of die size by 6.5% and cell array power consumption by 28%. Fast read/write of 60-ns cycle time as well as reliability improvement are realized by two high-speed error checking and correcting (ECC) techniques: 1) fast pre-parity calculation ECC sequence and 2) all-“0”-write-before-data-write scheme. Moreover, among nonvolatile memories reported so far, the 64 Mb chain FeRAM has achieved the highest read/write bandwidth of 200 MB/s with ECC. The chip size is 87.5 mm2 with average cell size of 0.7191 μm2.

Influence of Asymmetric Oxide Electrode Structures on the Interface Capacity and the Failure Mechanisms in PZT Thin Films

The influence of symmetric and asymmetric electrodes including SRO and IrO2 within the electrode structure on the imprint and fatigue behavior in sputtered and CSD derived PbZrxTi1 − xO2 (PZT) thin films is investigated. It is found that SRO buffer layers are needed within top and bottom electrode to improve the fatigue behavior. However, for improvement of the imprint behavior, only one SRO buffer layer within either top or bottom electrode is sufficient, whereas IrO2 reveals no improvement of the imprint behavior. Furthermore the direction dependence of the imprint behavior is examined. To examine the influence of the interface capacity on the fatigue mechanism in more detail, the capacity is measured for different PZT film thicknesses during fatigue treatment. It is shown that there is hardly any difference in interface capacity during fatigue.

Solder bump formation using electroless plating and ultrasonic soldering

Aluminum electrodes in the Si wafer were surface-treated in the sequence palladium activation, Ni-P electroless plating, ultrasonic soldering with Pb-1Sn solder, and dipping in Sn-37Pb to form second-stage solder bumps. The average bump height and the shear force were 20.3 mu m and 26.8 g/pad, respectively. The shear force did not decrease after the heating test (150 degrees C*1000 h) or thermal cycle test (-65 degrees C (--) room temperature (--) 150 degrees C, 300 cycles). Aluminum diffused to amorphous Ni-P through the Pd layer, Ni-Sn intermetallic compounds were formed at the Pb-1 Sn/Ni-P interface. The low-cost polyester tape-automated bonding was utilized to melt low temperature second solder on inner lead bonding. No bridge occurred when applying this technique to an LSI device with 376 electrodes, 100 mu m wide with 150 mu m pitch. >

Excellent properties of 0.15 micrometer ferroelectric PZT capacitor with SRO electrodes for future Gbit-scale ferams

Abstract Excellent ferroelectric properties of PZT capacitors with 0.15μ m lateral dimension were obtained for the first time using SrRuO3 electrode technology. The switching charge of the capacitor was not degraded even for the 0.15 μ m capacitor. The ferroelectric properties such as saturation, fatigue, and imprint characteristics were similar for the capacitors with 12 μ m to 0.15 μ m dimensions. We demonstrated that the SrRuO3 electrode technology could be used for the future Gbit-scale FeRAMs. An apparent increase in switching charge was also observed with decrease in capacitor size. The ferro-film around the top electrode may contribute to the increase of switching charge.

Comparison of Materials for the Ferroelectric Thin Film to be Integrated into High Density FeRAMs

Lead zirconate titanate (PZT) thin films with two different compositions have been used to fabricate integrated ferroelectric capacitors. The capacitors with the higher Ti content exhibited the more square hysteresis loops with peak 2Pr values of 67.3 μ C/ cm2 at room temperature. Static hysteresis loops are used to extract static coercive voltages for both compositions in the temperature range 25°C to 125°C. These static coercive voltages are used to extrapolate the imprint limited lifetime. The Ti rich composition exhibited the faster shift of the hysteresis loop during the imprint experiment resulting in a shorter extrapolated lifetime.