Iwao Kunishima

Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI

A nickel-monosilicide (NiSi) technology suitable for a deep sub-micron CMOS process has been developed. It has been confirmed that a nickel film sputtered onto n/sup +/- and p/sup +/-single-silicon and polysilicon substrates is uniformly converted into the mono-silicide (NiSi), without agglomeration, by low-temperature (400-600/spl deg/C) rapid thermal annealing. This method ensures that the silicided layers have low resistivity. Redistribution of dopant atoms at the NiSi-Si interface is minimal, and a high dopant concentration is achieved at the silicide-silicon interface, thus contributing to low contact resistance. This NiSi technology was used in the experimental fabrication of deep-sub-micrometer CMOS structures; the current drivability of both n- and p-MOSFETs was higher than with the conventional titanium salicide process, and ring oscillator constructed with the new MOSFETs also operated at higher speed. >

Ferroelectric Properties of Pb(Zi, Ti)O3 Capacitor with Thin SrRuO3 Films within Both Electrodes.

Ferroelectric properties of a Pb(Zi, Ti)O3 (PZT) capacitor with thin SrRuO3(SRO) films within both electrodes were investigated in detail. Thin SRO films of 10 nm thickness markedly improve the electrical performance, such as switching charge (Qsw), saturation characteristics of the hysteresis curve and imprint performance even at an elevated temperature. It should also be noted that there was no Qsw degradation after 5×1010 read/write cycles at 5 V. No leakage current increase after the test was observed. The results of transmission electron microscope (TEM) and electron dispersive X-ray (EDX) analyses also showed that there is no diffusion of either Sr or Ru in the PZT film. The Qsw increase can be explained by the model in which excess oxygen ions existing in the SRO films drift into the PZT due to the external electric field where they fill the oxygen vacancies in the PZT near the interfaces. We confirmed that the proposed electrode structure was a key to realizing highly reliable ferroelectric random access memories (FRAMs).

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes

An 87.7 mm2 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic capacitance sensing scheme, and dual metal plateline scheme - reduce bitline capacitance from 100 fF to 60 fF. As a result, a cell signal of ±220 mV is achieved even with the small cell size of 0.252 ¿m2. An 800 Mb/s/pin read/write bandwidth at 400 MHz clock is realized by installing SDRAM compatible DDR2 interface, and performance is verified by simulation. The internal power-line bounce noise due to 400 MHz clock operation is suppressed to less than 50 mV by an event-driven current driver, which supplies several hundreds of mA of current within 2 ns response. The precise timing and voltage controls are achieved by using the data stored in a compact FeRAM-fuse, which consists of extra FeRAM memory cells placed in edge of normal array instead of conventional laser fuse links. This configuration minimizes area penalty to 0.2% without cell signal degradation.

A 0.5-/spl mu/m, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor

A 0.5-/spl mu/m, 3-V operated, 1TIC, 1-Mbit FRAM with 160-ns access time has been developed. In FRAM, a reference voltage design using a ferroelectric capacitor is difficult because of the degradation due to fatigue, a chip-to-chip variation, and a temperature dependence. A variable reference voltage scheme is generated to solve this problem, boosting a fatigue-free and temperature-independent MOS reference capacitance by a driver. The driver is operated from a compact reference voltage generator that provides 32 equally divided voltages and occupies only half the layout area of a conventional one. During sense operation, memory-cell capacitance C/sub ferr/ is larger than reference-cell capacitance C/sub MOS/. A double word-line pulse scheme has also been developed to eliminate a bit-line capacitance imbalance in the bit-line pairs, where a memory cell and a reference cell are separated from the bit-line pairs during sense operation. A six-order improvement in imprint lifetime has been achieved by the new scheme.

A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode

A 64Mb chain FeRAM implemented in 0.13mum 3M CMOS technology is described. A quad-BL architecture reduces the die area by 6.5% and realizes 87.5mm2 die with an effective cell-size of 0.7191mum2 while eliminating BL-BL coupling noise. A high-speed ECC circuit and cell data write-back scheme achieves read/write cycle time of 60ns and 200MB/S burst

A sub-40 ns random-access chain FRAM architecture with a 768 cell-plate-line drive

This work demonstrates a prototype of nonvolatile chain ferroelectric RAM (chain FRAM), with fast compact cell-plate-line drive. A 16 kb chain FRAM test chip using 0.5 /spl mu/m 2-metal CMOS achieves 37 ns random-access time and 80 ns read/write cycle time at 3.3 V.

A 32-Mb chain FeRAM with segment/stitch array architecture

A 96mm/sup 2/, 32Mb chain FeRAM in 0.20/spl mu/m 3M CMOS and stacked capacitor technology is described. Cell efficiency of 65.6% is realized by compact memory cell structure and segment/stitch WL architecture. The word line power-on/off sequence protects the data from startup noise. A 3/spl mu/A standby current bias generator and compatible access mode SRAM are implemented for mobile applications.

A 76 mm/sup 2/ 8 Mb chain ferroelectric memory

An 8 Mb chain FeRAM uses 0.25 /spl mu/m 2-metal CMOS technology. A one-pitch-shift cell realizes 5.2 /spl mu/m/sup 2/ cell area. A chain architecture with a hierarchical wordline scheme gives 76 mm/sup 2/ die. Random access time is 40 ns, and cycle time is 70 ns at 3.0 V.

A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode

A 64-Mb chain ferroelectric RAM (chainFeRAM) is fabricated using 130-nm 3-metal CMOS technology. A newly developed quad bitline architecture, which combines folded bitline configuration with shield bitline scheme, eliminates bitline-bitline (BL-BL) coupling noise. The quad bitline architecture also reduces the number of sense amplifiers and activated bitlines, resulting in the reduction of die size by 6.5% and cell array power consumption by 28%. Fast read/write of 60-ns cycle time as well as reliability improvement are realized by two high-speed error checking and correcting (ECC) techniques: 1) fast pre-parity calculation ECC sequence and 2) all-“0”-write-before-data-write scheme. Moreover, among nonvolatile memories reported so far, the 64 Mb chain FeRAM has achieved the highest read/write bandwidth of 200 MB/s with ECC. The chip size is 87.5 mm2 with average cell size of 0.7191 μm2.

Homogeneous heteroepitaxial NiSi2 formation on (100)Si

The mechanism of NiSi2/Si interface formation on (100)Si is examined. The interface roughness between NiSi2 and Si strongly depends on the substrate impurity species. A smooth interface is formed on As-doped Si, but the interface is highly faceted on the {111} plane on BF2-doped Si. The covalent radius of the impurity atoms strongly affects the interface formation. An interfacial distorted layer is observed only at the NiSi2/As-doped Si interface. This distorted layer could reduce the lattice strain between NiSi2 and Si. These results demonstrate the possibility of realizing a homogeneous epitaxial interface.