Hiroyuki Kanaya

Ferroelectric Properties of Pb(Zi, Ti)O3 Capacitor with Thin SrRuO3 Films within Both Electrodes.

Ferroelectric properties of a Pb(Zi, Ti)O3 (PZT) capacitor with thin SrRuO3(SRO) films within both electrodes were investigated in detail. Thin SRO films of 10 nm thickness markedly improve the electrical performance, such as switching charge (Qsw), saturation characteristics of the hysteresis curve and imprint performance even at an elevated temperature. It should also be noted that there was no Qsw degradation after 5×1010 read/write cycles at 5 V. No leakage current increase after the test was observed. The results of transmission electron microscope (TEM) and electron dispersive X-ray (EDX) analyses also showed that there is no diffusion of either Sr or Ru in the PZT film. The Qsw increase can be explained by the model in which excess oxygen ions existing in the SRO films drift into the PZT due to the external electric field where they fill the oxygen vacancies in the PZT near the interfaces. We confirmed that the proposed electrode structure was a key to realizing highly reliable ferroelectric random access memories (FRAMs).

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes

An 87.7 mm2 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic capacitance sensing scheme, and dual metal plateline scheme - reduce bitline capacitance from 100 fF to 60 fF. As a result, a cell signal of ±220 mV is achieved even with the small cell size of 0.252 ¿m2. An 800 Mb/s/pin read/write bandwidth at 400 MHz clock is realized by installing SDRAM compatible DDR2 interface, and performance is verified by simulation. The internal power-line bounce noise due to 400 MHz clock operation is suppressed to less than 50 mV by an event-driven current driver, which supplies several hundreds of mA of current within 2 ns response. The precise timing and voltage controls are achieved by using the data stored in a compact FeRAM-fuse, which consists of extra FeRAM memory cells placed in edge of normal array instead of conventional laser fuse links. This configuration minimizes area penalty to 0.2% without cell signal degradation.

A 76 mm/sup 2/ 8 Mb chain ferroelectric memory

An 8 Mb chain FeRAM uses 0.25 /spl mu/m 2-metal CMOS technology. A one-pitch-shift cell realizes 5.2 /spl mu/m/sup 2/ cell area. A chain architecture with a hierarchical wordline scheme gives 76 mm/sup 2/ die. Random access time is 40 ns, and cycle time is 70 ns at 3.0 V.

Hydrogen induced imprint mechanism of Pt/PZT/Pt capacitor by low temperature hydrogen treatment

Abstract We found that low temperature and low pressure hydrogen annealing induced a severe voltage shift (imprint) of P – V hysteresis loop of Pt/PZT/Pt capacitor. The amount of shift depended on the annealing temperature and hydrogen pressure, and was about 0.8 V at 60°C, 10 min., 230 mTorr. From SIMS analyses, it was found that hydrogen accumulated at the interfaces between Pt and PZT after the annealing. The voltage shift increased with the increase in hydrogen concentration at the interfaces. The accumulated hydrogen is thought to reduce the PZT film and create oxygen vacancies at the interfaces, which act as fixed positive charges. The shift direction indicates that an internal bias field directed toward the bottom electrode was formed in the PZT film. This indicates that the hydrogen treatment resulted in a fixed positive charge being formed mainly at the interface between the top Pt and PZT. Detailed SIMS analyses revealed that PZT near the bottom electrode was conductive. Therefore, the oxygen va...

Excellent properties of 0.15 micrometer ferroelectric PZT capacitor with SRO electrodes for future Gbit-scale ferams

Abstract Excellent ferroelectric properties of PZT capacitors with 0.15μ m lateral dimension were obtained for the first time using SrRuO3 electrode technology. The switching charge of the capacitor was not degraded even for the 0.15 μ m capacitor. The ferroelectric properties such as saturation, fatigue, and imprint characteristics were similar for the capacitors with 12 μ m to 0.15 μ m dimensions. We demonstrated that the SrRuO3 electrode technology could be used for the future Gbit-scale FeRAMs. An apparent increase in switching charge was also observed with decrease in capacitor size. The ferro-film around the top electrode may contribute to the increase of switching charge.

Key process technology for high density 64M FeRAM and beyond

Difficulty to achieve high density FeRAMs with sub-micron ferroelectric capacitors is widely understood due to damage to the capacitors. Key process techniques such as high quality ferroelectric film deposition, electrode preparation, capacitor RIE and hydrogen barrier structure formation are introduced for 64M FeRAMs with sub micron high reliability PZT capacitors.

Characteristics of PZT films with SRO/Pt stack electrodes for high density mbit feram devices

Abstract Reliable PZT capacitors have been developed by using stable PZT sputtering technique and Pt/thinSRO(SrRuO3) stack electrodes. Introduction of SRO electrodes with no leakage current degradation is a key to realize reliable and scalable PZT capacitors. Roles of top electrode (TE) SRO and bottom electrode (BE) SRO were investigated respectively from reliability and process damage points of view. The SRO works as hydrogen resistant electrodes, fatigue free interfaces and nucleation sites for perovskite formation. Relationship between SRO crystallinity and PZT electrical properties was elucidated. Templates made of thin SRO were found to function as barrier layers against diffusion of Pb and Ru from BE resulting in new possible cell structures.