Kristof Kellens

Integration of Vertical Carbon Nanotube Bundles for Interconnects

Carbon nanotubes (CNTs) are considered a promising material for interconnects for future generation microchips. The integration of vertical CNT in a processing environment is evaluated in this work. Extrapolated performances of CNT-based interconnects are compared with existing technologies at different hierarchy levels including the limitations of present deposition methods for copper and tungsten. For practical implementation, CNT bundles were selectively grown into contact holes using physical vapor deposited and electrochemical deposited cobalt or nickel catalysts. A polishing step was used to control the CNT length after embedding the CNT into an oxide matrix. A CNT metal decoration method based on electrodeposition is presented, which can be used to assess the yield of electrically conductive CNT as well as to form top contacts for electrical characterization. Finally, the importance of having suitable and robust structures for evaluating the integration process is highlighted after the electrical characterization of CNT in a nanoprober station.

CMP process optimization for improved compatibility with advanced metal liners

As copper interconnect structures are shrinking with each technology node novel metals other than PVD Ta(N)/Ta are being introduced as barrier materials. These materials act as seed enhancement layers and enable the Cu filling of the narrowest structures. However, the integration of such metals into the manufacturing of sub-35 nm wide Cu lines produces several challenges which need to be addressed. One of these challenges is the compatibility of the interconnect metals with the copper Chemical Mechanical Polishing (CMP) step. In particular, corrosion issues and Cu defectivity in the trenches need to be controlled. An evaluation of the compatibility of the CMP slurries with the new incorporated materials therefore becomes extremely important. Our work shows that by optimizing the CMP process and selecting compatible slurries, novel metals such as CVD Co (combined with a Ta(N) barrier) are promising candidates for the metallization of sub-35 nm lines.

Process control & integration options of RMG technology for aggressively scaled devices

We report on aggressively scaled RMG-HKL devices, with tight low-V_T distributions [σ(V_Tsat) ~ 29mV (PMOS), ~ 49mV (NMOS) at L_gate~35nm] achieved through controlled EWF-metal alloying for NMOS, and providing an in-depth overview of its enabling features: 1) physical mechanisms, model supported by TCAD simulations and analysis techniques such as TEM, EDS; 2) process optimizations implementation: oxygen sources reduction, control of RF-PVD TiAl/TiN ratio and reduced H_gate, also impacting stress induced in the channel. Additional key features: 1) Al vs. W as fill-metal, with careful liner/barrier materials selection and tuning yielding well-behaved devices with tight R_gate distributions down to L_gate~20nm, and enabling both PMOS and NMOS low-VT values for high aspect-ratio gates (H_gate~60nm, L_gate≥30nm); 2) wet-etch vs. siconi clean for dummy-dielectric removal, with HfO₂ post-deposition N₂-anneal resulting in substantial BTI improvement without EOT or low-field/peak mobility penalty, and good noise response.

Dielectric Reliability of 50 nm Half Pitch Structures in Aurora® LK

The dielectric reliability of Aurora® LK (k = 3.0) material has been evaluated on a 50 nm half pitch test structure. These were fabricated using a double patterning scheme and TiN metal hard mask. The introduction of a suitable post-etch residue removal step and close-coupled processing between Cu electroplating and chemical mechanical polishing were found to be key for achieving high yield. Median time-dependent dielectric lifetime of 10 years is reached at an electrical field of 1.4 MV/cm, comparable to earlier reported results with SiO2 as dielectric. The reliability performance is found to be significantly layout dependent with corners being weak points due to local field enhancement.

Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-k last devices and enabling a simplified scalable CMOS integration scheme

We report on aggressively scaled replacement metal gate, high-k last (RMG-HKL) planar and multi-gate fin field-effect transistor (FinFET) devices, systematically investigating the impact of post high-k deposition thermal (PDA) and plasma (SF6) treatments on device characteristics, and providing a deeper insight into underlying degradation mechanisms. We demonstrate that: 1) substantially reduced gate leakage (JG) and noise can be obtained for both type of devices with PDA and F incorporation in the gate stack by SF6, without equivalent oxide thickness (EOT) penalty; 2) SF6 enables improved mobility and reduced interface trapped charge density (Nit) down to narrower fin devices [fin width (WFin) ≥ 5 nm], mitigating the impact of fin patterning and fin sidewall crystal orientations, while allowing a simplified dual-effective work function (EWF) CMOS scheme suitable for both device architectures; 3) PDA yields smaller, in absolute values, PMOS threshold voltage |VT|, and substantially improved reliability behavior due to reduction of bulk defects.

Integration and Dielectric Reliability of 30 nm Half Pitch Structures in Aurora® LK HM

Aurora® LK HM (k=3.2) material has been successfully integrated into 30 nm half pitch structures. This material outperforms Aurora® LK (k=3.0) in terms of breakdown field strength and mechanical properties. Scaling of the physical vapor deposition (PVD) based barrier/seed process and adjusting of the barrier chemical mechanical polishing (CMP) overpolish condition were yield enabling factors. No degradation of the breakdown field upon reducing half pitch is observed down to 30 nm for line lengths up to at least 1 mm. The median time-dependent dielectric breakdown (TDDB) lifetime, as evaluated on a 1 mm 35 nm half pitch parallel line structure, exceeds 10 years at an electrical field of 2.6 MV/cm.

Metallization of sub-30 nm interconnects: Comparison of different liner/seed combinations

Narrow trenches with Critical Dimensions down to 17 nm were patterned in oxide using a sacrificial FIN approach and used to evaluate the scalability of TaN/Ta, RuTa, TaN + Co and MnOx metallization schemes. So far, the RuTa metallization scheme has proved to be the most promising candidate to achieve a successful metallization of 25 nm interconnects, providing high electrical yields and a good compatibility with the slurries used during CMP.

Use of MIR-FTIR and k-value Measurements to Assess Potential Solutions to Reduce Damage During Porous Low-k Integration

Multiple Internal Reflection (MIR) FTIR is used to assess the impact of potentially damaging BEOL integration process steps such as Chemical Mechanical Polishing (CMP) and NH3-based plasmas on a k=2.55 porous interlayer dielectric. The NH3 plasma is found to be very damaging, and a He plasma prior to the same NH3 plasma leads to a damage reduction. The impact of CMP is also confirmed and leads to an equivalent k-value degradation as a He + NH3 plasma. In order to reduce the integration damage, the addition of a low-k protective cap layer (k=3.3) is proposed. The required thickness to avoid impact from CMP and NH3-based plasmas is found to be 10 nm after CMP (Kstack=2.60 with 10 nm cap). As a result, those process steps are no longer a concern with this integration route.

Thermal and Plasma Treatments for Improved (Sub-)1nm EOT Planar and FinFET-based RMG High-k Last Devices and Enabling a Simplified Scalable CMOS Integration Scheme

RMG High-k Last Devices and Enabling a Simplified Scalable CMOS Integration Scheme A. Veloso, G. Boccardi, L.-Å. Ragnarsson, Y. Higuchi, H. Arimura, J. W. Lee, E. Simoen, M. J. Cho, Ph. J. Roussel, V. Paraschiv, X. Shi, T. Schram, S. A. Chew, S. Brus, A. Dangol, E. Vecchio, F. Sebaai, K. Kellens, N. Heylen, K. Devriendt, H. Dekkers, A. Van Ammel, T. Witters, T. Conard, I. Vaesen, O. Richard, H. Bender, R. Athimulam, T. Chiarella, A. Thean, and N. Horiguchi Imec, assignee at Imec from Panasonic, Kapeldreef 75, 3001 Leuven, Belgium; also at K. U. Leuven, Belgium Tel.: +32-16-28 17 28, Fax: +32-16-28 17 06, Email: Anabela.Veloso@imec.be

Cu/Low-k Thickness Measurement for Advanced Cu CMP Process Development and Control

We investigated a wafer level Cu/low-k thickness measurement technique and compared it to the electrical and surface profiling techniques. With this optical technique, we can achieve a comprehensive within-die and within-wafer Cu/low-k thickness monitoring which allows for a more accurate Cu CMP process control in advance Cu/low-k damascene structures.