Kuo Ming Wu

On-Resistance Degradation Induced by Hot-Carrier Injection in LDMOS Transistors With STI in the Drift Region

In this letter, on-resistance (<i>R</i> _on) degradation induced by hot-carrier injection in n-type lateral DMOS transistors with shallow-trench isolation (STI) in the drift region is investigated. <i>R</i> _on decreases at the beginning of stress, but <i>R</i> _on increases as the stress time is increased. Experimental data and technology computer-aided-design simulation results reveal that hot-hole injection and trapping at the STI corner closest to the channel are responsible for the <i>R</i> _on reduction. The damage caused by hot-electron injection at the STI edge closest to the drain is responsible for the <i>R</i> _on increase.

An Investigation on Anomalous Hot-Carrier-Induced On-Resistance Reduction in n-Type LDMOS Transistors

In this paper, on-resistance (<i>R</i> _on) degradation induced by hot-carrier injection in n-type lateral diffused metal-oxide-semiconductor transistors with shallow trench isolation (STI) in the drift region is investigated. <i>R</i> _on unexpectedly decreases under medium- and high-gate voltage (<i>V</i> _gs) stress conditions. According to experimental data and technology computer-aided-design simulation results, the mechanisms responsible for anomalous <i>R</i> _on shift are proposed. When the device is stressed under medium <i>V</i> _gs, hot-hole injection and trapping occur at the STI edge closest to the channel, resulting in <i>R</i> _on reduction. Interface trap generation (¿<i>N</i> _it) occurs at the STI edge closest to the channel and nearby drift region, leading to <i>R</i> _on increase. For the device stressed under high <i>V</i> _gs, <i>R</i> _on reduction is also attributed to hole trapping at the STI corner closest to the channel. ¿<i>N</i> _it created by hot-electron injection at the STI edge closest to the drain dominates device characteristics and leads to <i>R</i> _on increase eventually. Based on the proposed <i>R</i> _on degradation mechanisms, an <i>R</i> _on degradation model is discussed and verified with experimental data.

Effect of Drift-Region Concentration on Hot-Carrier-Induced

In this letter, hot-carrier-induced on-resistance (Ron) degradation in lateral DMOS transistors with different n-type drift-drain (NDD) region concentration is investigated. Increasing NDD concentration results in greater bulk (Ib) and gate currents (Ig), but Ron degradation is improved. Technology computer-aided design simulations reveal that high NDD concentration increases impact-ionization rate in accumulation (related to Ib increase) and channel regions (related to Ig increase) but reduces impact-ionization rate in spacer region. Charge-pumping data confirm that hot-carrier-induced interface state created in the spacer region is reduced, leading to improved Ron degradation in high-NDD-concentration device.

R_{\rm on}

Hot-carrier-induced device degradation in n-type high-voltage drain-extended MOS (DEMOS) devices stressed under high drain voltage and high gate voltage (Vg) is investigated. Charge pumping data and technology computer-aided-design simulation results reveal that hot-carrier-induced interface state formation in the gate overlapped shallow trench isolation region is responsible for device degradation. Furthermore, an unexpected high saturation region drain current (Id(sat)) degradation (close to on-resistance degradation) is observed. The occurrence of quasi-saturation under high Vg bias is the cause of significant Id(sat) degradation. The results presented in this paper suggest that severe Id(sat) degradation may become a reliability concern for devices exhibiting the quasi-saturation phenomenon.

Degradation in nLDMOS Transistors

The phenomena and mechanisms of hot-carrier-induced threshold-voltage (<i>V</i> _T) shift in high-voltage p-type laterally diffused MOS (LDMOS) transistors are investigated. At low-|<i>V</i> _gs| (absolute value of gate voltage) stress condition, electrons are injected and trapped in the gate oxide at the channel region near the drain, resulting in <i>V</i> _T increase (Delta|V_T| < 0). At high-|<i>V</i> _gs| stress condition, however, severe <i>V</i> _T decrease (Delta|V_T| > 0) is found after stress. Experimental results suggest that donor-type interface traps created by hole injection in the channel region is the dominant factor for <i>V</i> _T decrease.

Convergence of Hot-Carrier-Induced Saturation Region Drain Current and On-Resistance Degradation in Drain Extended MOS Transistors

In this letter, the dynamic turn-on mechanism of the n-MOSFET under high-current-stress event is investigated by using a real-time current and voltage measurement. Results reveal the existence of ldquoself-consistent effect,rdquo i.e., the turn-on region of the parasitic n-p-n bipolar can change from one region to another region and increases with the stress current (ID). Furthermore, experimental data show that the minimum substrate potential to sustain a stable snapback phenomenon is 0.9 V and increases with ID instead of 0.6-0.8 V and independent of ID as reported in early literatures.

Mechanisms of Hot-Carrier-Induced Threshold-Voltage Shift in High-Voltage p-Type LDMOS Transistors

In this letter, on-resistance RON degradation in lateral double-diffused MOS transistors is observed when the device is operated under off-state avalanche-breakdown condition. Although interface states and positive oxide-trapped charges are created near the drain, interface-state generation is identified to be the main degradation mechanism. Technology computer-aided design simulation suggests that the driving force of damage is breakdown-induced hole injection. Experimental data show that RON degradation has the tendency to saturate, in agreement with the saturation of interface-state generation and oxide-trapped charges data extracted by charge-pumping measurement.

Dynamic Turn-On Mechanism of the n-MOSFET Under High-Current Stress

Channel length (Lch) dependence of hot-carrier-induced degradation in n-type drain extended metal-oxide-semiconductor (DEMOS) transistors stressed under high drain voltage and high gate voltage is investigated. On-resistance degradation is reduced in longer Lch device, however, threshold voltage shift (ΔVT) is greater. Charge pumping data reveal that electron trapping in gate oxide above channel region is responsible for ΔVT. Simulation results show that longer Lch device exhibits enhanced vertical electric field (Ey), i.e., enhanced hot-electron injection, in channel region due to the alleviation of Kirk effect. Results presented in this letter reveal that enhanced ΔVT driven by enhanced channel Ey may become a serious reliability concern in DEMOS transistors with longer Lch.

off -State Avalanche-Breakdown-Induced on -Resistance Degradation in Lateral DMOS Transistors

On-resistance (Ron) degradation induced by avalanche breakdown is investigated in lateral double-diffused MOS transistors with different dosages of n-type drain drift (NDD) region. Ron degradation is caused by interface state and positive oxide-trapped charge created near the drain-side polygate edge. The device with a higher NDD dosage generates less interface state but more positive oxide-trapped charge, leading to a reduction in Ron degradation. Such a result reveals that increasing NDD dosage reduces avalanche-breakdown-induced Ron degradation.

Channel length dependence of hot-carrier-induced degradation in n-type drain extended metal-oxide-semiconductor transistors

The mechanism of hot-carrier-induced degradation in n-type lateral diffused metal-oxide-semiconductor (LDMOS) transistors is investigated. Experimental data reveal that hot-electron injection induced interface state generation in channel region is the main degradation mechanism. Since gate current (Ig) consists mainly of electron injection, Ig correlates well with device degradation. As a result, a lifetime prediction method based on Ig is presented for the purpose of projecting hot-carrier lifetime in LDMOS transistors.