Shiang Yu Chen

On-Resistance Degradation Induced by Hot-Carrier Injection in LDMOS Transistors With STI in the Drift Region

In this letter, on-resistance (<i>R</i> _on) degradation induced by hot-carrier injection in n-type lateral DMOS transistors with shallow-trench isolation (STI) in the drift region is investigated. <i>R</i> _on decreases at the beginning of stress, but <i>R</i> _on increases as the stress time is increased. Experimental data and technology computer-aided-design simulation results reveal that hot-hole injection and trapping at the STI corner closest to the channel are responsible for the <i>R</i> _on reduction. The damage caused by hot-electron injection at the STI edge closest to the drain is responsible for the <i>R</i> _on increase.

An Investigation on Anomalous Hot-Carrier-Induced On-Resistance Reduction in n-Type LDMOS Transistors

In this paper, on-resistance (<i>R</i> _on) degradation induced by hot-carrier injection in n-type lateral diffused metal-oxide-semiconductor transistors with shallow trench isolation (STI) in the drift region is investigated. <i>R</i> _on unexpectedly decreases under medium- and high-gate voltage (<i>V</i> _gs) stress conditions. According to experimental data and technology computer-aided-design simulation results, the mechanisms responsible for anomalous <i>R</i> _on shift are proposed. When the device is stressed under medium <i>V</i> _gs, hot-hole injection and trapping occur at the STI edge closest to the channel, resulting in <i>R</i> _on reduction. Interface trap generation (¿<i>N</i> _it) occurs at the STI edge closest to the channel and nearby drift region, leading to <i>R</i> _on increase. For the device stressed under high <i>V</i> _gs, <i>R</i> _on reduction is also attributed to hole trapping at the STI corner closest to the channel. ¿<i>N</i> _it created by hot-electron injection at the STI edge closest to the drain dominates device characteristics and leads to <i>R</i> _on increase eventually. Based on the proposed <i>R</i> _on degradation mechanisms, an <i>R</i> _on degradation model is discussed and verified with experimental data.

Convergence of Hot-Carrier-Induced Saturation Region Drain Current and On-Resistance Degradation in Drain Extended MOS Transistors

Hot-carrier-induced device degradation in n-type high-voltage drain-extended MOS (DEMOS) devices stressed under high drain voltage and high gate voltage (Vg) is investigated. Charge pumping data and technology computer-aided-design simulation results reveal that hot-carrier-induced interface state formation in the gate overlapped shallow trench isolation region is responsible for device degradation. Furthermore, an unexpected high saturation region drain current (Id(sat)) degradation (close to on-resistance degradation) is observed. The occurrence of quasi-saturation under high Vg bias is the cause of significant Id(sat) degradation. The results presented in this paper suggest that severe Id(sat) degradation may become a reliability concern for devices exhibiting the quasi-saturation phenomenon.

Mechanisms of Hot-Carrier-Induced Threshold-Voltage Shift in High-Voltage p-Type LDMOS Transistors

The phenomena and mechanisms of hot-carrier-induced threshold-voltage (<i>V</i> _T) shift in high-voltage p-type laterally diffused MOS (LDMOS) transistors are investigated. At low-|<i>V</i> _gs| (absolute value of gate voltage) stress condition, electrons are injected and trapped in the gate oxide at the channel region near the drain, resulting in <i>V</i> _T increase (Delta|V_T| < 0). At high-|<i>V</i> _gs| stress condition, however, severe <i>V</i> _T decrease (Delta|V_T| > 0) is found after stress. Experimental results suggest that donor-type interface traps created by hole injection in the channel region is the dominant factor for <i>V</i> _T decrease.

Anomalous Hot-Carrier-Induced Increase in Saturation-Region Drain Current in n-Type Lateral Diffused Metal–Oxide–Semiconductor Transistors

Anomalous increase in saturation-region drain current I_d(sat) but serious on-resistance degradation (decrease in linear-region drain current) is observed in n-type high-voltage lateral diffused MOS transistors stressed under medium gate voltage V_g. However, I_d(sat) is degraded for the devices stressed under low and high V_g. Experimental data reveal that two competing mechanisms are responsible for the shift of I_d(sat). One is the interface state N_it formation in the N^- drift region. The other is the N_it formation in the channel region. The former mechanism leads to the anomalous increase in I_d(sat), whereas the latter mechanism causes the to decrease. Experimental data and technology computer-aided-design simulations confirm that the impact ionization rate of the device is enhanced if significant N_it formation in the N^- drift region is present. According to the results presented in this paper, significant formation in the drift region is identified to be the main mechanism responsible for the anomalous increase in I_d(sat).

Channel length dependence of hot-carrier-induced degradation in n-type drain extended metal-oxide-semiconductor transistors

Channel length (Lch) dependence of hot-carrier-induced degradation in n-type drain extended metal-oxide-semiconductor (DEMOS) transistors stressed under high drain voltage and high gate voltage is investigated. On-resistance degradation is reduced in longer Lch device, however, threshold voltage shift (ΔVT) is greater. Charge pumping data reveal that electron trapping in gate oxide above channel region is responsible for ΔVT. Simulation results show that longer Lch device exhibits enhanced vertical electric field (Ey), i.e., enhanced hot-electron injection, in channel region due to the alleviation of Kirk effect. Results presented in this letter reveal that enhanced ΔVT driven by enhanced channel Ey may become a serious reliability concern in DEMOS transistors with longer Lch.

Mechanism and lifetime prediction method for hot-carrier-induced degradation in lateral diffused metal-oxide-semiconductor transistors

The mechanism of hot-carrier-induced degradation in n-type lateral diffused metal-oxide-semiconductor (LDMOS) transistors is investigated. Experimental data reveal that hot-electron injection induced interface state generation in channel region is the main degradation mechanism. Since gate current (Ig) consists mainly of electron injection, Ig correlates well with device degradation. As a result, a lifetime prediction method based on Ig is presented for the purpose of projecting hot-carrier lifetime in LDMOS transistors.

Effects of Drift-Region Design on the Reliability of Integrated High-Voltage LDMOS Transistors

Effects of drift-region design on the hot-carrier reliability of n-channel integrated high-voltage lateral diffused MOS (LDMOS) transistors are investigated. LDMOS devices with various dosages of n-type drain drift (NDD) implant and various drift-region lengths (Ld) are studied. Results show that higher NDD dosage can reduce hot-carrier induced on-resistance (Ron) degradation. The shift in damage location is suggested to be the main cause. In addition, longer Ld can reduce Ron degradation significantly because of less lateral electric field. Our analysis indicates that higher NDD dosage and longer Ld are effective for improving the device lifetime of the LDMOS transistors.

Investigation of Hot-Carrier-Induced Degradation Mechanisms in p-Type High-Voltage Drain Extended Metal–Oxide–Semiconductor Transistors

Hot-carrier-induced degradation in p-type drain extended metal–oxide–semiconductor (DEMOS) devices is investigated. The gate voltage biased at the second substrate current peak produces the most device degradation. The generation of interface state (ΔNit) in the channel region, ΔNit in the drift region under poly-gate, and negative oxide-trapped charge (ΔNot) in the drift region outside poly-gate are responsible for device parameter degradation. ΔNit in the channel region causes threshold voltage and maximum transconductance degradation. ΔNot in the drift region outside poly-gate leads to the increase of linear drain current (Idlin) at the beginning of stress. ΔNit in the drift region under poly-gate results in the turnaround behavior of |Idlin| shift as the stress time is longer.

Effect of Gate Voltage on Hot-Carrier-Induced On-Resistance Degradation in High-Voltage n-Type Lateral Diffused Metal-Oxide-Semiconductor Transistors

The phenomenon and mechanism of hot-carrier-induced on-resistance (Ron) degradation for the n-type lateral diffused metal–oxide–semiconductor (MOS) transistors stressed under various gate voltages (Vg) are investigated. Ron degradation of the device is found to be attributed to the interface state (Nit) generation in the N- drift region. Moreover, Ron degradation is almost identical for the devices stressed under medium Vg and high Vg, despite the fact that bulk current of the device is much greater at high Vg bias. Such an anomalous Ron degradation is suggested to be the result of two combined factors: the magnitude of impact ionization rate and Nit generation efficiency.