S. L. Hsu

Anomalous Reduction of Hot-Carrier-Induced On-Resistance Degradation in n-Type DEMOS Transistors

Anomalous hot-carrier degradation phenomenon was observed in a 0.5-mum 12-V n-type drain-extended MOS transistors (N-DEMOS) with various n-type drain-drift (NDD) implant dosage. Under the same stress condition, the device with a higher NDD dosage produces a higher substrate current, a slightly higher transconductance degradation, but a lower ON-resistance (RON) degradation. Two degradation mechanisms are identified from the analysis of the electrical data and two-dimensional device simulations. The first mechanism is hot-electron injection in the accumulation region near the junction of the channel and accumulation regions. The second mechanism is hot-hole injection in the accumulation region near the spacer. This injection of hot holes creates a positive-charge trapping in the gate oxide, resulting in negative mirror charges in the accumulation region that reduces RON. The second mechanism is identified to account for the anomalous lower RON degradation

Time-Dependent Drain- and Source-Series Resistance of High-Voltage Lateral Diffused Metal–Oxide–Semiconductor Field-Effect Transistors during Hot-Carrier Stress

In this paper, a new reverse transconductance method for investigating the effect of hot-carrier degradation on high-voltage (HV) lateral diffused metal–oxide–semiconductor field-effect transistors (LDMOSFETs) is presented. This new method can extract asymmetric drain and source series resistance separately with only one single device. By using this extraction method in HV LDMOSFETs before and after the application of hot-carrier stress, drain series resistance is extracted and found to increase while source series resistance remains the same. In addition, the threshold voltage and subthreshold slope suffer no degradation after the application of hot-carrier stress. Therefore, it is suggested that the current degradation in HV LDMOSFETs after the application of hot-carrier stress is not due to the damage under the channel but is due to the drift region under the spacer oxide. This is confirmed by the simulation results of a two-dimensional (2D) simulator. In addition, the differences in hot-carrier degradation between HV LDMOSFETs and low-voltage lightly doped drain (LV LDD) MOSFETs are also discussed in detail.

Effect of hot-carrier-induced interface states distribution on linear drain current degradation in 0.35 μm n-type lateral diffused metal-oxide- semiconductor transistors

The mechanisms of hot-carrier-induced linear drain current (Idlin) degradation in a 0.35μm n-type lateral diffused metal-oxide-semiconductor transistor, operating at a nominal voltage of 12V, is investigated. Results and analysis show that the location of hot-carrier-induced interface states varies with stress gate voltage. Stress-induced interface states located in accumulation region under polygate have little effect on Idlin degradation. As a result, interface states located in drain-side spacer region dominate Idlin degradation when interface states located in channel region are negligible.

Effects of Drift-Region Design on the Reliability of Integrated High-Voltage LDMOS Transistors

Effects of drift-region design on the hot-carrier reliability of n-channel integrated high-voltage lateral diffused MOS (LDMOS) transistors are investigated. LDMOS devices with various dosages of n-type drain drift (NDD) implant and various drift-region lengths (Ld) are studied. Results show that higher NDD dosage can reduce hot-carrier induced on-resistance (Ron) degradation. The shift in damage location is suggested to be the main cause. In addition, longer Ld can reduce Ron degradation significantly because of less lateral electric field. Our analysis indicates that higher NDD dosage and longer Ld are effective for improving the device lifetime of the LDMOS transistors.

Effect of Gate Voltage on Hot-Carrier-Induced On-Resistance Degradation in High-Voltage n-Type Lateral Diffused Metal-Oxide-Semiconductor Transistors

The phenomenon and mechanism of hot-carrier-induced on-resistance (Ron) degradation for the n-type lateral diffused metal–oxide–semiconductor (MOS) transistors stressed under various gate voltages (Vg) are investigated. Ron degradation of the device is found to be attributed to the interface state (Nit) generation in the N- drift region. Moreover, Ron degradation is almost identical for the devices stressed under medium Vg and high Vg, despite the fact that bulk current of the device is much greater at high Vg bias. Such an anomalous Ron degradation is suggested to be the result of two combined factors: the magnitude of impact ionization rate and Nit generation efficiency.

Characteristics and improvement in hot-carrier reliability of sub-micrometer high-voltage double diffused drain metal-oxide-semiconductor field-effect transistors

The hot-carrier reliability of 12 V high-voltage n-channel double diffused drain metal–oxide–semiconductor (DDDMOS) field-effect transistors with various n-type double diffusion (NDD) implant dosages is investigated. A high NDD implant dosage results in a high substrate current; however, on-resistance (Ron) degradation is low. The damage location shifting toward the channel is responsible for this unexpected low Ron degradation. Technology computer-aided design (TCAD) simulation and charge pumping measurements are carried out to identify the damage location. Our analysis results reveal that an increase in NDD dosage is effective for improving the reliability of the DDDMOS field-effect transistors.

An Investigation on Hot-Carrier Reliability and Degradation Index in Lateral Diffused Metal-Oxide-Semiconductor Field-Effect Transistors

The hot-carrier-induced degradation in the high-voltage n-type lateral diffused metal–oxide–semiconductor (LDMOS) field-effect transistor is investigated. Interface state generation caused by hot-electron injection in the channel region is identified to be the main degradation mechanism. Since the gate current (Ig) consists mainly of the electron injection, Ig correlates well with the hot-carrier lifetime of the device. The impact of varying device layout parameter on the performance and hot-carrier lifetime of the device are also evaluated. Such an analysis can achieve a better design of LDMOS transistors when considering both device performance and hot-carrier reliability.

High voltage NPN-bipolar transistor using P/sup +/-buried layer in BiCMOS process

An easy to implement high voltage NPN transistor is integrated in a low voltage (LV) thin (4.5 /spl mu/m) epi-layer BiCMOS process. In this high voltage (HV) bipolar transistor, the conventional N/sup +/-buried layer of the collector is replaced with a P/sup +/-buried layer. The breakdown voltage is higher than 90 V. High current gain (>140), high Early voltage (>500 V), and high frequency response (>1.3 GHz) are also obtained.