Won-sang Song

50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications

A 90 nm generation logic technology with Cu/low-k interconnects is reported. 50 nm transistors are employed using gate oxide 1.3 nm in thickness and operating at 1.0 V. High speed transistors have drive currents of 870 /spl mu/A/pm and 360 /spl mu/A//spl mu/m for NMOS and PMOS respectively, while generic transistors have currents of 640 /spl mu/A//spl mu/m and 260 /spl mu/A//spl mu/m respectively. Low power process using high-k gate dielectrics and SOI process are also provided in this technology. The low-k SiOC material with 2.9 in the k value is used for 9 layers of dual damascene Cu/low-k interconnects. The effective k (k/sub eff/) value of interconnect is about 3.6. Fully working 6-T SRAM cell with an area of 1.1 /spl mu/m/sup 2/ and SNM value of 330 mV is obtained. For MIM capacitor, voltage coefficient of capacitance is less than 20 ppm/V.

High performance pMOSFET with BF/sub 3/ plasma doped gate/source/drain and S/D extension

A BF/sub 3/ Plasma doping (PLAD) process has been utilized in source/drain/gate and shallow S/D extension for high performance 0.18 /spl mu/m pMOSFET. Gate oxide reliability, drain current, and transconductance of the pMOSFET with BF/sub 3/ PLAD are remarkably improved compared to those of BF/sub 2/ ion implanted devices. Cobalt salicide formation is also compatible with the plasma doped S/D junction.

Characterization of Cu extrusion failure mode in dual-damascene Cu/low-k interconnects under electromigration reliability test

With low electrical resistivity and superb electromigration properties relative to Al, Cu is considered an exemplary candidate for metallization in logic devices. The electromigration characteristics, however, are highly contingent upon the test criteria, which in turn vary with the test structure and/or materials, e.g. inter/intra-metal dielectrics. The thermal mismatch stress existing between low-k SiOF and Cu, for instance, degrades the metal adhesion and curtails the device lifetime (Riedel, 1997). Such deleterious stress may also induce an extrusion mode failure, resulting in an unstable EM data with high sigma (Ennis, 2000) and an improper estimation of via lifetime. In this study, we identify a few pertinent factors involved in the formation of Cu extrusion mode failures in a Cu-SiOF dual damascene structure, and propose a possible underlying mechanism. Extrusion-free specimens, i.e. once the problem is eliminated, show an activation energy of about 0.81 eV, and the EM failures are limited to the via regions.

Advanced i-PVD barrier metal deposition technology for 90 nm Cu interconnects

An advanced i-PVD(ionized physical vapor deposition) barrier metal deposition technology has been developed for 90 nm Cu interconnects. The feature of this technology is to re-sputter the thick barrier metal at the contact/trench bottom, which was deposited by i-PVD, and attach the re-sputtered barrier metal to the sidewall. By using this technology, it is possible to obtain relatively thin bottom and thick sidewall coverage and thus a more conformal deposition. This technology is shown to be very effective in both lowering via resistance and improving reliabilities of 90 nm Cu interconnects embedded in SiOC-type low-k(k=2.9) inter-metal dielectric.

Re-defining reliability assessment per new intra-via Cu leakage degradation

By stressing via-incorporated interconnect structures, we demonstrate for the first time the accelerated deterioration of leakage reliability relative to conventional biased-thermal-stressing of Cu line/space modules. Electric field analyses confirm said finding, invoking the need to correspondingly adjust the reliability testing criteria to ensure the most conservative lifetime projection. Two important collateral consequences include leakage aggravation with Ar plasma treatment prior to barrier metal deposition and bias direction dependence of intra-via or line-via reliability.

Electromigration reliability of dual damascene copper interconnect with different IMD structures

Electromigration behavior of dual damascene Cu interconnect has been investigated comparing PE-TEOS SiO/sub 2/ with fluorine doped SiO/sub 2/ (FSG). MTFs of FSG in both line and contact EM tests were significantly shorter than those of PE-TEOS. The higher compressive stress and fluorine of FSG dielectric are considered to affect the EM reliability performance of the confined Cu interconnect.

A HSQ-based inorganic sacrificial via filler-assisted 90 nm-node Cu/low-k OSG dual damascene process integration

Integrating FSG dual damascene interconnects using MSQ-based sacrificial via filler has been previously shown. When applying such via filler to a Cu/low-k OSG integration, however, the requisite O/sub 2/-ashing induces an inevitable damage to the low-k OSG due to the challenge in selectively eliminating such filler using conventional wet chemistry. By employing an inorganic HSQ that can readily be removed per dilute fluoric acid cleaning in low-k OSG structure, we demonstrated not only a more viable technology with lower defect density at each process step, e.g., photolithography and etching, but also a simpler process that selectively removes the filler material relative to the existing technology based on MSQ and/or organic fillers.

Cost-effective "BARC/resist-via-fill free" integration technology for 0.13 /spl mu/m Cu/low-k

Demonstrates the first successful integration scheme free of BARC/resist via-fill that not only significantly simplifies the overall process complexity, but also reduces cost and process instabilities by employing an OSG (k=2.9)/ HDP-FSG dual ILD structure in conjunction with our proprietary plasma induced polymeric etch stopper (PIPS) in a 7-metal level 0. 13 /spl mu/m design node. The via poisoning problem and low selectivity of etch stopper were overcome by optimizing ILD structure and PIPS etch process. The electrical characteristics and reliability results indicate that the current integration scheme is highly manufacturable.