L. S. Huang

Intrinsic hot-carrier degradation of nMOSFETs by decoupling PBTI component in 28nm high-k/metal gate stacks

For the first time, a new decoupling method of PBTI component from hot-carrier (HC) stress is proposed. It is found that the HC degradation is contributed from both PBTI and intrinsic HC component. Using the power-law time exponent of Vt shift in PBTI and HC, the intrinsic HC degradation can be extracted. In addition, a physical model for HC degradation in high-k/metal gate (HK/MG) device has been suggested.

Gate Leakage Characteristics for 28 nm HfZrO x pMOSFETs After DPN Process Treatment With Different Nitrogen Concentration

Feasibly adjusting the gate leakage and the device performance in balance is an obvious challenge. Additionally, stacking the high-k dielectric as a gate dielectric in nanonode process is an appreciate way to promote the drive current in pMOSFETs. Unfortunately, the amount of oxygen vacancy or the interfacial layer thickness on the surface channel will possibly reduce the drive current owing to the increasing magnitude of threshold voltage and increase in the gate leakage degrading the standby capability in circuit operation. To retard this disadvantage or intensify the device quality, applying a lower pressure decoupled-plasma nitridation process to obliquely reform the amount of oxygen vacancy is a feasible alternative. On the basis of tested data, the nitridation treatment in a higher N2 concentration is better than that in a lower one, such as the improvement of gate leakage, drive current, subthreshold swing, and channel mobility in pMOSFETs, especially for shorter channel-length devices.

Heat stress exposing performance of deep-nano HK/MG nMOSFETs using DPN or PDA treatment

Abstract Decoupled plasma nitridation (DPN) or post-deposition annealing (PDA) process after high-k (HK) deposition to repair the bulk traps or the oxygen vacancy in gate dielectric is an impressive choice to raise up the device performance. Before heat stress, the electrical performance in drive current, channel mobility and subthreshold swing with both treatments was approximate, except the higher annealing atmosphere causing the thicker interfacial layer and reducing the overall related dielectric constant. After temperature stress, the electrical performance for all of the tested devices was slightly deteriorated. The degradation degree for electrical performance with PDA treatment group was the worst case due to NH3 atmosphere forming Si–H bond on the channel surface, which was broken after stress and produced more interface state reflected with the increase of subthreshold swing.

Gate Leakage for 28 nm Stacked HfZrO x Dielectric of p-Channel MOSFETs After Decoupled Plasma Nitridation Treatment With Annealing Temperatures

Choosing a plasma nitridation treatment with some annealing technique incorporated into the gate engineering is helpful to fix the existence of oxygen vacancy and promote the crystallization temperature in high-k dielectric. Here is the higher annealing atmosphere as a whole providing the better drive current in p-channel metal-oxide-semiconductor field-effect transistors, compared with the lower one. The interface traps for the former, however, is slightly greater than the latter, causing a higher gate leakage in the middle electrical field operated at inversion mode. This phenomenon is more obvious in the tested short-channel device. A sandwich type of HfOx/ZrOy/HfOx as gate dielectric at 28 nm node process is a fine selection to withstand or decrease the possibility of the formation of micro- or nanocrystallization increasing the gate leakage.

Early effect exposing performance of 28nm HK/MG pMOSFETs under PDA or DPN nitridation treatment

Incorporating a high-k dielectric and metal gate engineering at deep-nano node process is a trend to promote the drive current of MOSFET devices. Nevertheless lots of challenges crowdedly reveal either process technologies or device model establishment. To reduce the gate leakage and enhance the device reliability, the nitridation process after high-k deposition will be utilized, but causing the difficulty in device model construction. One of the issues is Early effect which is not intersected at one point. The vertical field in gate node hugely contributes its influence in the entire electrical field in device operation.

Trend of subthreshold swing with DPN process for 28nm N/PMOSFETs

Although decoupled plasma nitridation (DPN) post high-k dielectric deposition shows the better threshold voltage shift than post deposition anneal (PDA), the non-adequate plasma nitrogen (N) concentration and anneal temperature still can dominate the device performance. Using these two variables to probe the impact of HK deposition integrity and the interface quality between channel and gate dielectric is an undetected and published topic. In the experiment, the lower N-concentration and higher anneal temperature is beneficial to the higher drive current and lower threshold for NMOSFET. However, the PMOSFET prefers the lower anneal temperature as well as lower N-concentration. Additionally, the phenomena for the combination of DPN process and strain engineering causing the non-uniform trend distribution of subthreshold swing with device channel lengths were exposed.

Kink effect for 28 nm n–channel field–effect transistors after decoupled plasma nitridation treatment with annealing temperatures

The kink effect of drain leakage based on gated diode measurement metrology for the tested nMOSFETs with 28 nm HK/MG, gate–last and PDA or DPN nitridation processes was observed at VG around −0.6 V when the gate voltage was swept from −Vcc to 0.2 volt as VD = 0.1 V. Nevertheless, this interesting phenomenon was not evident as the gate voltage was reversely swept from 0.2 volt to -Vcc. The chief mechanism in speculation can be illustrated by the electrons coming from drain inducing capture–and–emission behaviour by the channel interface traps near the drain junction. While VG changes from −Vcc towards +0.2 V, interface states near valence band become lower than Fermi–level of silicon substrate. Electrons flow from drain to fill these interface states so that drive current (ID) increases. On the contrary, as VG changes from +0.2 V to −Vcc, the trapped electrons are recombined with holes from substrate so that ID is not affected. This kink effect for all of tested devices is not very distinct far and near. When the Poole–Frenkel (P–F) tunnelling electrons coming from gate to drain are evident in leakage, especially at the long–channel device, this effect will be probably counteracted, exhibited at the electrical characteristics of PDA group.

Electrical quality of 28nm HK/MG MOSFETs with PDA and DPN treatment

On the basis of tested data, the performance of NMOSFETs with PDA treatment in drive current, S.S. values and channel mobility is superior to that with DPN treatment. Comparing two nitridation treatment processes at the same annealing temperature, it seems that PDA proving the hydrogen to fix the dangling bond on the channel surface is more beneficial for device performance before the reliability test. Furthermore, the capability in healing of oxygen vacancy of gate dielectric is little better than that with DPN, illustrating in lower gate leakage, especially as the channel length is narrowed down.

CLM effect for 28nm stacked HK nmosfets after DPN treatment with different annealing temperatures

In this work, it can be seen that the effect of channel length modulation for NMOSFETs under high-k/metal gate deposition depicts a minor deviation with different nitridation annealing temperatures. This consequence, however, strongly correlates to the channel length and the gate voltage playing as a vertical field. As the channel length is narrowed down, the horizontal field coming from drain voltage on the channel is increased more and compresses the effective channel length, reflecting on the Early voltage VA. In the past, all of ID vs. VD curves after extrapolation would approach an identical intersection point. But this phenomenon should be modified more right now.