Liang Zhang

3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver

A 120-mV/sub ppd/ low swing pulse receiver is presented for AC coupled interconnect (ACCI). Using this receiver, 3Gb/s chip-to-chip communication is demonstrated through a wire-bonded ACCI channel with 150-fF coupling capacitors, across 15-cm FR4 microstrip lines. A test chip was fabricated in TSMC 0.18-/spl mu/m CMOS technology and the driver and pulse receiver dissipate 15-mW power per I/O at 3 Gb/s, with a bit error rate less than 10/sup -12/. First-time demonstration of a flip-chip ACCI is also presented, with both the AC and DC connections successfully integrated between the flipped chip and the multichip module (MCM) substrate by using the buried bump technology. For the flip-chip ACCI, 2.5 Gb/s/channel communication is demonstrated across 5.6 cm of transmission line on a MCM substrate.

Driver pre-emphasis techniques for on-chip global buses

By using current-sensing differential buses with driver pre-emphasis techniques, power dissipation is reduced by 26.0%-51.2% and peak current is reduced by 63.8%, compared to conventional repeater insertion techniques, for 10mm long buses in TSMC 0.25/spl mu/m technology. This proposed architecture lowers the worst coupling capacitance to total capacitance ratio to 14.4%. It only requires 7.9% more bus routing area than single-ended designs for a 16-bit bus, and saves all of the repeater placement blockages. To further verify that the driver pre-emphasis techniques can also be applied to voltage-mode single-ended buses, a test chip in TSMC 0.18/spl mu/m technology was fabricated and measured.

A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling

This paper describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25-mum complementary metal-oxide-semiconductor (CMOS) technology attains an aggregate signaling data rate of 32 Gb/s over 5-10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5-48.7-mW power dissipation was measured for signal activity above 0.1, equivalent to 0.80-1.52 pJ/b. This work demonstrates a 15.0%-67.5% power reduction over a conventional single-ended voltage-mode static bus while reducing delay latency by 28.3% and peak current by 70%. The proposed bus architecture is robust against crosstalk noise and occupies comparable routing area to a reference static bus design.

A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver

A new differential pulse receiver is demonstrated for AC coupled interconnect (ACCI), which enables the highest data rate, at 6Gb/s/channel (36Gb/s aggregate), for capacitively coupled systems using pulse signaling. The system works across FR4 printed circuit board (PCB) interconnect lengths of up to 30cm with coupling capacitors from 95fF to 165fF, while dissipating only 1.97mW/Gbps for the entire differential transceiver (0.83pJ/bit for the transmitter and 1.23pJ/bit for the receiver)

A 32Gb/s On-chip Bus with Driver Pre-emphasis Signaling

A 16-bit on-chip bus with driver pre-emphasis fabricated in 0.25mum CMOS technology attains an aggregate signaling data rate of 32Gb/s over 5-10mm long lossy interconnects while reducing delay latency by 28.3%, power by 15.0%, and peak current by 70% over a conventional single-ended voltage-mode static bus. The proposed bus is robust against crosstalk noise and occupies comparable routing area to a reference static bus design

Differential current-mode signaling for robust and power efficient on-chip global interconnects

A global interconnect scheme with better current return path control is presented for accurate inductance analysis and robust interconnect design. High performance is obtained by using differential signaling, current-mode sensing, bridge termination, and driver pre-emphasis.

Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses

This paper demonstrates that driver preemphasis technique can be used for on-chip global buses to increase signal channel bandwidth. Compared to conventional repeater insertion techniques, driver preemphasis saves repeater layout complexity and reduces power consumption by 12%-39% for data activity factors above 0.1. A driver circuit architecture using voltage-mode preemphasis technique was tested in 0.18-mum CMOS technology for 10-mm long interconnects at 2 Gb/s

Simplified delay design guidelines for on-chip global interconnects

Based on the effective attenuation constant approximation of distributed RLC lines, simplified design guidelines are presented dealing with the line characteristics, termination, and delay estimation of on-chip global interconnects. RC delay models are verified to be still accurate for a wide range of parameters conventionally considered inductive. A new closed-form RLC delay formula is developed when RC models are inadequate. The formula works for both voltage and current-mode signaling and exhibits 10% accuracy of SPICE simulation. This work is suitable for global routing topologies and iterative layout optimization.