Lionel Trojman

Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions

The authors demonstrate high-performing n-channel transistors with a HfO2/TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 Aring, a leakage current of 1.5 A/cm2 at VG=1 V, a peak mobility of 190 cm2/Vmiddots, and a drive-current of 815 muA/mum at an off-state current of 0.1 muA/mum for VDD=1.2 V. Identical gate stacks processed with a 1000-degC spike anneal have a higher peak mobility at 275 cm2/Vmiddots, but a 5-Aring higher EOT and a reduced drive current at 610 muA/mum. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 degC) for a ten-year lifetime, whereas positive-bias temperature-instability measurements indicate a sufficient lifetime for operating voltages below 0.75 V

RF Split Capacitance–Voltage Measurements of Short-Channel and Leaky MOSFET Devices

In this letter, the feasibility of split-capacitance-voltage (C-V) measurements in the RF range is demonstrated. These RF/split-C-V measurements show excellent agreement with the values obtained by the low-frequency conventional technique but without presenting any noticeable degradation due to gate leakage

Mobility and Dielectric Quality of 1-nm EOT HfSiON on Si(110) and (100)

In this paper, we study the mobility and dielectric quality of MOSFETs with 1-nm Equivalent Oxide Thickness (EOT) grown on substrates with different crystallographic orientations: (100) and (110). Measurement techniques based on RF split CVs (150 MHz) on short-channel devices (down to 80 nm) are used to extract the electrical parameters. Despite the different oxidation growth rates expected by changing the substrate orientation, we obtain similar EOT values even for thin dielectrics (1 nm). Further identical gate overlaps are found regardless of the substrate orientation. The mobility in (110) substrate shows a large improvement for p-MOS. This improvement is independent of the EOT (down to 1 nm) and the length scaling. Although larger interface states were observed by charge pumping for the (110) devices, low-temperature mobility study suggests that the remote charge scattering, and therefore, the gate stack quality is the same.

Novel, Effective and Cost-Efficient Method of Introducing Fluorine into Metal/Hf-based Gate Stack in MuGFET and Planar SOI Devices with Significant BTI Improvement

In this work, we propose a new, effective, and cost-efficient method of introducing fluorine into metal/Hf-based gate stack of planar and multi-gate devices (MuGFET), resulting in significant improvements in both NBTI and PBTI characteristics. The key advantage of this method is that it uses the SF6-based metal gate etch for F introduction, requiring no extra implantation steps. In addition to the significant BTI improvement with the novel method, we also demonstrate, for the first time, better Vth control and increased drive current on MuGFET devices.

Fundamentals and extraction of velocity saturation in sub-100nm (110)-Si and (100)-Ge

A novel RFCV-technique is applied to directly quantify the short channel devices at high Vds, enabling parameter extraction like velocity saturation and critical field. This technique is applied to benchmark Si (110) and Si(100) as well as Ge devices. Similarities and crucial differences between short channel parameters in Si and Ge are discussed.

Effectiveness of Nitridation of Hafnium Silicate Dielectrics: A Comparison Between Thermal and Plasma Nitridation

The results of a systematic study on the effects of nitrogen incorporation into (60%Hf/40%Si) hafnium silicate/SiO2 dielectric stacks are presented. Several nitridation methods and processes are compared as a function of the highest performing SiO2 interlayer/high-k/post-deposition anneal combination on each wafer. It is shown that nitrogen incorporation results in a reduction in not only leakage current density but also maximum drive current, and carrier mobility. The relative increase in leakage current density with measurement temperature is independent of nitridation method or process, which indicates that phase separation may not be a problem for 2-nm hafnium silicate dielectrics. Depending on exact performance requirements, a nitridation step may not be necessary, as its benefits are limited (on ~2.0 nm equivalent oxide thickness films) to a factor of 2 reduction in leakage current density, with 4% and 7% reduction in mobility and drive current, respectively.

Velocity and Mobility Investigation in 1-nm-EOT HfSiON on Si (110) and (100)—Does the Dielectric Quality Matter?

One of the fundamental questions for gate-stack scaling is whether the low-field mobility measured in long-channel devices is a good proxy for short-channel performance at high field. In this paper, we thoroughly investigate low- and high-field transports (velocity and mobility) in 1-nm-EOT high-kappa materials on Si (100) and (110) down to cryogenic temperature. It is shown that scattering in Si substrate dominates the transport at high field, thus enabling relaxation of the low-field-mobility requirement for future scaling below 1-nm EOT.

Nitrogen Incorporation in HfSiO(N)/TaN Gate Stacks: Impact on Performances and NBTI

Performance and negative-bias temperature instability (NBTI) on atomic-layer-deposited HfSiON metal-gated pMOSFETs are investigated. The impact of nitrogen incorporation either with plasma nitridation or NH3 anneal is studied and compared to the nonnitrided stacks. The capacitance equivalent thickness reduction that is observed in nitrided stacks is compensated by the slight decrease of the hole mobility for the same gate overdrive, resulting in no improvement of the performance. On the other hand, it is shown that nitridation strongly enhances NBTIs in these devices. Based on these results, the necessity of nitrogen incorporation in thin HfSiON/metal gate stacks should be reconsidered.

On the Impact of Defects Close to the Gate Electrode on the Low-Frequency

This letter studies the impact of defects close to the gate electrode side on low-frequency 1/f noise in the drain and gate current. Defects are selectively introduced by deposition of a submonolayer of HfO2 dielectric, which induce a large Fermi-level pinning on the gate. Contrary to the common belief that defects at the Si/SiO2 interface are the dominant effect on 1/f noise, defects at the interface and fluctuations in the poly-Si charge are also important.

\hbox{1}/f

Hf-based gate dielectrics layers with EOT≪1nm are actively investigated for 22nm node and beyond. EOT scalability of these films is simultaneously achieved by reducing the high-k thickness as well as optimizing the N-profile into the thin film. For Hf-based layers electron traps in the upper part of the bandgap have been a major concern for nMOSFETs since they cause VT-instability and affect mobility [1]. With the scaling of EOT to 1 nm and below, the impact of these traps has, however, disappeared [2]. Electron traps have never been considered a potential problem for PMOS because at negative bias they are always efficiently discharged. We found, however, that in PMOS with EOT ˜1 nm, a large hysteresis at high field is observed in the ID-VG characteristics, while no hysteresis is measured on the corresponding NMOS devices (on the same wafer) (Fig. 1). In this work we will prove by an advanced charge pumping technique that the hysteresis in PMOS is caused by hole traps in the high-k layer. Furthermore, we show how NBTI defects are correlated with such hole traps. Hole trap density depends on the Hf- and N-profile in the film, being larger for Hf-rich films.