I. Ferain

Multi-gate devices for the 32nm technology node and beyond

Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased VT statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32 nm technology node on planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET based multi-gate devices for the 32 nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed.

Experimental evidence of short-channel electron mobility degradation caused by interface charges located at the gate-edge of triple-gate FinFETs

The mechanism responsible for the short-channel electron mobility (e

Treshold voltage modulation in FinFET devices through Arsenic Ion Implantation into TiN/HfSiON gate stack

mobility) abnormal degradation in n-type tall fins multiple-gate field-effect transistors (MuGFETs) has been identified. RF-CV measurement, mobility extraction, and 1/f noise measurements have been performed and point to a larger process related density of traps (N t) at the gate edges. These traps and their distribution along the channel give a common and consistent explanation for the channel dependence of the mobility and the normalized noise degradation and for the threshold voltage roll off

Metal gate thickness optimization for MuGFET performance improvement

We have demonstrated NMOS FinFET devices with a Vt of 0.33V through As implantation into TiN. The method allows for multiple Vt FinFET devices with Vts of 0.33V, 0.55V (NMOS) and -0.35V (PMOS) through just one As implantation step into lOnm TiN. The NMOS Vt can be further modulated by adjusting the As implantation dose. Further optimization of the cap, implantation and annealing conditions will be needed to keep the implantation damage away from the gate dielectric.

Metal Gate Technology using a Dy 2 O 3 Dielectric Cap Approach for multiple-V T in NMOS FinFETs

In this paper, we investigate the dependence between the performance of multiple-gate FETs (dasiaMuGFETspsila) and the thickness of their plasma-enhanced-ALD (PE-ALD) TiN gate electrode. We show that very thin PE-ALD-TiN gate electrodes allow improved short channel effect (SCE) control and enhanced performance in n-channel MuGFETs without mobility modification. Based on the electrical characterization of MuGFETs and the physical analysis of their gate stacks, we show that the thickness of the TiN metal gate affects the nature of its reaction with the gate dielectric. This, in return, results into threshold voltage (VT) and gate inversion thickness (Tinv) modifications which can explain performance enhancement in n-FETs without any performance loss in p-FETs.

Multiple-Vt FinFET devices through La 2 O 3 dielectric capping

In this work, we investigate the possibility of achieving low V_T nMOS FinFETs with single metal gate by using a dysprosium oxide (Dy₂O₃) cap layer inserted between gate dielectric and metal. We determine an optimum ratio between Dy₂O₃ and SiO₂ gate dielectric thicknesses for low nMOS V_T with good process margin and no loss in performance and reliability.

MUGFET - alternative transistor architecture for 32 nm CMOS generation

In this work, the possibility of achieving low Vt nMOS FinFET transistors through the use of a La₂O₃ dielectric cap, and the ability of co-integrating La₂O₃ capping with medium and low Vt pFinFET devices are investigated. A significant improvement in device performance was shown for thin La₂O₃ capping with CVD TaN electrode.

Reduction of the anomalous VT behavior in MOSFETs with high-κ/metal gate stacks

In this paper, the suitability of the MUGFET technology as an alternative device architecture for 32 nm CMOS generation is discussed. In particular, the requirements for the MUGFET devices with focus on FIN geometry, gate stack, and junctions are analyzed. Technological challenges related to the processing of MUGFET devices such as, FIN and gate patterning, junctions and spacer formation, are also presented