Lovell B. Wiggins

2.5D and 3D technology challenges and test vehicle demonstrations

Three-dimensional (3D) chip integration with through-silicon-vias (TSVs) can enable system benefits of enhanced performance, power efficiency, and cost reduction leveraging micro-architecture designs such as 2.5D silicon packages and 3D die stacks. 2.5D silicon packages and 3D die stacks structures integrated in modules each have unique technical challenges but each can provide system benefits including lower latency and higher bandwidth compared to traditional packaging solutions. Additional system benefits using 2.5D or 3D integration can include product miniaturization or increased function in the same size product. Leveraging proper design and micro-architecture for a system application, 3D technology can aide chip manufacturability for lower costs, sub-component heterogeneous integration, modular design and sub-component design reuse, which can reduce development expense and decrease time to market. 2.5D and 3D technology can reduce interconnection length between circuits leading to lower power consumption and lower latency as well as increase the number of interconnections which supports increased bandwidth to traditional 2D off chip interconnection. Appropriate design ground rules, clocking, and electrical models should match well defined technology attributes such as TSVs and silicon to silicon interconnection electrical parametrics. In addition a wafer test methodology for known good die (KGD) and high yield assembly integration approach are important to obtain integrated 2.5D and 3D modules. For complex 3D integration, proper consideration for module or integrated die stacked with TSVs and Si to Si interconnection may require redundancy and an integral repair methodology. 2.5D and 3D technology challenges may include an increase in the power delivery and cooling requirements to meet the increased circuit density and power density of these structures. For small, low power applications such as mobile devices, 2.5D and 3D technology can provide substantial benefit through both performance benefit and power savings and lead to longer battery life for the same function. For some high performance and high power applications, the 2.5D approach simplifies heterogeneous die integration without requiring leading to increases power density and heat removal cooling density. Whereas some high performance and high power applications using 3D technology may require extensive planning for power delivery with localized power regulation and specialized cooling approaches to avoid excessive in die stack temperatures while taking advantage of performance gains that these short links between heterogeneous die can provide. 3D die stacks using multi-core processors and wide I/O DRAM, eDRAM, SRAM or cache stacks can provide high bandwidth, performance improvements with lower latency. In addition to the power delivery and thermal challenges of 2.5D and 3D described above, there are 3D fabrication and industry compatibility challenges. Technology challenges include wafer integration and finishing with TSVs, test for known-good-die (KGD), assembly and module integration. Infrastructure compatibility and use of newly evolving industry standards such as Semi-3D standards for wafer handling and JEDEC standards for wide I/O memory to name two examples. Standards for wafer shipping are underway and other 3D compatibility standards are being defined over time. This research paper describes key challenges to enable systems using 2.5D and 3D technology. The paper also highlights progress and results for 2.5D and 3D hardware demonstrations and gives an outlook on future demonstrations.

3D Chip stacking with 50 μm pitch lead-free micro-c4 interconnections

3D integration, using fine-pitch and high density vertical interconnects (TSVs), has been drawing considerable interest due to its promise for higher performance and smaller form factor. As the number of I/O increases and the pitch size decreases, interconnect joining process and reliability become critical in the assembly of 3D chip stacks. In this study, 3D chip stacks with more than 48,000 Pb-free solder micro-bump interconnects at 50 μm pitch were assembled and the joint reliability evaluated. Multiple bonding processes were developed, enhanced and characterized by investigating the influence of various bonding parameters such as atmosphere, compression mode and temperature profile on the joint formation. Various test vehicle sizes with multiple layers of thinned die were successfully assembled using the enhanced bonding profile. Underfilling of the narrow gaps between the stack dies was demonstrated using underfills with fine-particle fillers. The assembly yield and interconnection parasitic resistance was quantitatively studied as a function of the number of die layers. The reliability silicon die stacks integrated into modules with organic laminates was characterized by thermal cycling tests.

Low-temperature heat capacity and entropy of chalcopyrite (CuFeS2): estimates of the standard molar enthalpy and Gibbs free energy of formation of chalcopyrite and bornite (Cu5FeS4)

Abstract The heat capacity of CuFeS2 (chalcopyrite) was measured between 6.3 and 303.5 K. At 298.15 K, Cp,mo and Smo(T) are (95.67±0.14) J·K−1·mol−1 and (124.9±0.2) J·K−1·mol−1, respectively. From a consideration of the results of two sets of equilibrium measurements we conclude that ΔfHmo(CuFeS2, cr, 298.15 K) = −(193.6±1.6) kJ·mol−1 and that the recent bomb-calorimetric determination by Johnson and Steele (J. Chem. Thermodynamics 1981, 13, 991) is in error. The standard molar Gibbs free energy of formation of bornite (Cu5FeS4) is −(444.9±2.1) kJ·mol−1 at 748 K.

Electrical fails specific to Pressure Cooker Test

This paper emphasizes the need for thorough failure analysis and understanding of the failure mechanism to utilize the Pressure Cooker Test (PCT). The high relative humidity extracted bromide ions from the Flip Chip Plastic Ball Grid Array (FCPBGA), which catalyzed growth of unusual tin oxides and drove the extrusion of solder causing shorts.

NiFe-based Ball-limiting-metallurgy (BLM) for microbumps at 50μm pitch in 3D chip stacks

In this work, Pb-free microbumps at 50μm pitch with NiFe-based Ball-limiting-metallurgy (BLM) are fabricated and tested. Detailed microstructural analysis has been performed, which shows a uniform thin layer (~0.2μm) of FeSn2 Intermetallic Compound (IMC) is formed between the Pb-free solder and NiFe BLM after the first reflow. In comparison, the NiCuSn IMC can grow more than 2μm in microbumps with the conventional Ni BLM or solder-caped Cu pillar after the first reflow. An excessive lateral “thermal-undercut” has been discovered in NiFe BLM structures during solder reflows due to good edge wettability of NiFe. A dual-layer BLM structure is proposed and demonstrated to mitigate the “thermal-undercut”. Moreover, addition of NiFe layer on a micro-Cu pillar structures have been demonstrated and characterized.