Kris Croes

Efficient system exploration and synthesis of applications with dynamic data storage and intensive data transfer

Matisse is a design flow intended for developing embedded systems characterized by tight interaction between control and data-flow behavior, intensive data storage and transfer, dynamic creation of data, and stringent real-time requirements. Matisse bridges the gap from a system specification, using a concurrent object-oriented language, to an optimized embedded single-chip HW/SW implementation. Matisse supports stepwise system-level exploration and refinement, memory architecture exploration, and gradual incorporation of timing constraints before going to traditional tools for HW synthesis, SW compilation, and HW/SW interprocessor communication synthesis. Application of Matisse on telecom protocol processing systems shows significant improvements in area usage and power consumption.

Matisse: a system-on-chip design methodology emphasizing dynamic memory management

MATISSE is a design environment intended for developing systems characterized by a tight interaction between control and data-flow behavior, intensive data storage and transfer, and stringent real-time requirements. Matisse bridges the gap from a system specification, using a concurrent object-oriented language, to an optimized embedded single-chip hardware/software implementation. Matisse supports stepwise exploration and refinement of dynamic memory management, memory architecture exploration, and gradual incorporation of timing constraints before going to traditional tools for hardware synthesis, software compilation, and inter-processor communication synthesis. With this approach, specifications of embedded systems can be written in a high-level programming language using data abstraction. Application of MATISSE on telecom protocol processing systems in the ATM area shows significant improvements in area usage and power consumption.

Design Technology co-optimization for N10

Design-Technology co-optimization becomes a key knob to enable CMOS scaling. In this work we evaluate the technology options including lithography options as well as device options that are considered to enable N10 scaling by exploring their impact on representative designs such as standard cells, SRAM and analog contexts. This paper illustrates that the design angle needs to be considered early in the development of a technology node. This design assessment and decisions start from lithography constraints and options to power/performance, area and cost, all of which create the Design-Technology Co-Optimization space.

Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study

New technologies for manufacturing 3D Stacked ICs offer numerous opportunities for the design of complex and effcient embedded systems. But these technologies also introduce many design options at system/chip design level, hard to grasp during the complete design cycle. Because of the sequential nature of current design practices, designers are often forced to introduce design margins to meet required specications, resulting in sub-optimal designs. In this paper we introduce new design methodology and practical tool chain, called PathFinding Flow, that can help designers to easily trade-off between different system level design choices, physical design and/or technology options and understand their impact on typical design parameters such as cost, performance and power. Proposed methodology and the tool chain will be demonstrated on a practical case study, involving fairly complex Multi-Processor System-on-Chip using Network-on-Chip for communication medium. With this example we will show how High-Level Synthesis can be used to quickly move from high-level to RTL models, necessary for accurate physical prototyping for both computation and communication. We will also show how the possibility of design iteration, through the mechanism of feedback based on physical information from physical prototyping, can improve design performance. Finally, we will show how we can move in no time from traditional 2D to 3D design and how we can measure benets of such design choice.

TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes

This paper proposes TEASE (Technology Exploration and Analysis for SoC-level Evaluation), a framework to systematically analyze and evaluate system design in finFET-based technology node. The proposed framework combines both lithography and electrical constraints of a particular technology node to optimize the standard cell library performance. Growing complexity of logic design at nodes below 20nm causes to adopt a design style that can embrace the simplicity required to enable manufacturing, along with a process technology that can be finely tuned to the desired performance constraints. Additionally, the introduction of finFET based devices poses a new challenge for the designers to come up with an efficient standard cell template. The proposed framework can be used to detect the technology constraints that act as the bottleneck for the enablement of design at these advanced nodes. Results presented in this paper show by optimizing these bottlenecks we can improve the performance of a standard cell library significantly. Furthermore, adapting to such an analysis framework at an early stage of technology development helps to take the design constraints into the decision loop for realization of technology research into real products.

Hardware and a Tool Chain for ADRES

Until recently, only a compiler and a high-level simulator of the reconfigurable architecture ADRES existed. This paper focuses on the problems that needed to be solved when moving from a software-only view on the architecture to a real hardware implementation, as well as on the verification process of all involved tools.

Design strategy for integrating DSA via patterning in sub-7 nm interconnects

In recent years, major advancements have been made in the directed self-assembly (DSA) of block copolymers (BCPs). As a result, the insertion of DSA for IC fabrication is being actively considered for the sub-7nm nodes. At these nodes the DSA technology could alleviate costs for multiple patterning and limit the number of litho masks that would be required per metal layer. One of the most straightforward approaches for DSA implementation would be for via patterning through templated DSA, where hole patterns are readily accessible through templated confinement of cylindrical phase BCP materials. Our in-house studies show that decomposition of via layers in realistic circuits below the 7nm node would require at least many multi-patterning steps (or colors), using 193nm immersion lithography. Even the use of EUV might require double patterning in these dimensions, since the minimum via distance would be smaller than EUV resolution. The grouping of vias through templated DSA can resolve local conflicts in high density areas. This way, the number of required colors can be significantly reduced. For the implementation of this approach, a DSA-aware mask decomposition is required. In this paper, our design approach for DSA via patterning in sub-7nm nodes is discussed. We propose options to expand the list of DSA-compatible via patterns (DSA letters) and we define matching cost formulas for the optimal DSA-aware layout decomposition. The flowchart of our proposed approach tool is presented.

Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuits

Abstract. Major advancements in the directed self-assembly (DSA) of block copolymers have shown the technique’s strong potential for via layer patterning in advanced technology nodes. Molecular scale pattern precision along with low cost processing promotes DSA technology as a great candidate for complementing conventional photolithography. Our studies show that decomposition of via layers with 193-nm immersion lithography in realistic circuits below the 7-nm node would require a prohibitive number of multiple patterning steps. The grouping of vias through templated DSA can resolve local conflicts in high density areas, limiting the number of required masks, and thus cutting a great deal of the associated costs. A design method for DSA via patterning in sub-7-nm nodes is discussed. We present options to expand the list of usable DSA templates and we formulate cost functions and algorithms for the optimal DSA-aware via layout decomposition. The proposed method works a posteriori, after place-and-route, allowing for fast practical implementation. We tested this method on a fully routed 32-bit processor designed for sub-7 nm technology nodes. Our results demonstrate a reduction of up to four lithography masks when compared to conventional non-DSA-aware decomposition.

Impact of process variability on BEOL TDDB lifetime model assessment

We investigate the impact of process variability on BEOL TDDB lifetime model assessment. The change in functional form of TDDB lifetime plots due to line-to-line variability and line-edge-roughness has been quantified in the field range in which long term TDDB measurements have been obtained. We found that the Pearson R2, which is used as a measure of linearity of a lifetime plot, did not significantly change due to process variability. Where process variability has a significant effect on TDDB and needs to be taken into account during data analysis, our simulations suggest that it does not have an impact on BEOL TDDB lifetime model assessment. We propose that the conclusions from recent literature reports which point in the direction of a less conservative model compared to the √E-model are valid, although they do not take process variability into account during the data analysis.

Intrinsic reliability of local interconnects for N7 and beyond

The intrinsic Time Dependent Dielectric Breakdown properties of the spacer between gate and first level local interconnects are assessed for dielectrics and spacings compatible with N7 and beyond. The intrinsic reliability properties down to 3nm thickness of standard LPCVD Si3N4- and PECVD Si3N4-films as well as more advanced Al2O3- and low-k CVD SiN-layers have been studied using imecs pcap test vehicle. It turned out that the leakage current of the more advanced films are not worse compared to the more standard layers. Besides, their reliability performance, in terms of Emax, is the same or even slightly better. Down to 3nm thickness, Emax-values higher than 3.5MV/cm were obtained for all dielectrics studied. Fundamental insight in the breakdown processes is obtained by testing a wide thickness range (3-20nm) for the PECVD Si3N4-layer, where higher Emax and QBD were found for the thinner layers, suggesting that less damage is created by electrons when injecting them into thinner films (fluence driven failure mechanism). A difference in leakage and reliability when applying different polarities suggests different mechanisms playing a role when the electrons are injected from the interconnect or from the gate metal. Finally, field simulations at critical locations in the studied structure were used to assess places of higher local field enhancement. We found that at these places, the fields were still lower compared to the Emax-values of the intrinsic films, suggesting that scalability down to 3nm spacer thickness is intrinsically reliable.