M. Cimino

Design of a 0.9 V 2.45 GHz Self-Testable and Reliability-Enhanced CMOS LNA

A self-testable and highly reliable low noise amplifier designed in 0.13 m CMOS technology is presented in this paper. This reliable LNA could be used to design the front-end of critical nodes in wireless local area networks to ensure data transmission. The LNA test, based on a built-in self test methodology, monitors its behavior. The test circuit is composed of one sensor and one biasing voltage sensor, and it offers high fault coverage. The high reliability is ensured by the use of redundancies. The LNA works under a 0.9 V supply voltage and the test chip has RF characteristics suitable for 802.11b/g applications. Parametric faults are injected and detected to demonstrate the efficiency of the BIST circuitry. Thanks to the switching on redundant blocks, performances are maintained and hence this proves the reliability of the methodology proposed.

A Robust 130nm-CMOS Built-In Current Sensor Dedicated to RF Applications

An otherwise well-known ratiometric built-in current sensor (BICS) dedicated to monitor the current of analog and mixed-signal building blocks highlights a dependency with regards to technology discrepancy. In this paper we present a design methodology that allows to dramatically reduce the dependency, yielding to a new version of this BICS. Taking advantage of a 130 nm VLSI CMOS technology, the BICS proposed has a peak-to-peak dispersion lower than 10 % of its output full-scale range. It makes it more suitable to implement the test functionality while maintaining the initial BICS intrinsic performances. The built-in self test methodology is illustrated by monitoring the supply current of a low-noise amplifier (LNA). Measurements confirm the BICSs low sensitivity to process variations and its transparency relative to the circuit under test (CUT)

A Low-Power and Low Silicon Area Testable CMOS LNA Dedicated to 802.15.4 Sensor Network Applications

A low noise amplifier designed in a 0.13 mum CMOS VLSI technology is presented, which has self-test capabilities in order to monitor its behavior within a ZigBee sensor network during its life time. The silicon area required for both the built-in self test circuitry and the LNA has been optimized in order to reduce the overall cost of the function, using a shunt-feedback topology. The LNA provides a measured power gain of 10 dBm and a 2.4 dB noise figure, while consuming only 3.6 mW under a 1.2 V power supply. The test chip has been designed for robustness to fit a mass production requirements. The test chip demonstrates that the addition of the self-test circuitry has no impact on the LNA performances, while being efficient.

A bulk-controlled temperature and power supply independent CMOS voltage reference

A temperature and supply voltage independent voltage reference is presented. The design is carried out using the STM 65 nm CMOS process. An analytical study is carried out to show the feasibility to adjust the temperature independent output voltage controlling the biasing of the bulk of one transistor. A feedback is introduced in order to do so. Post-layout simulations confirm the analytical results. The circuit works with a 0.9 V supply voltage and a total power consumption of 27 muW. A temperature coefficient as low as 9 ppm in the temperature range [-50degC;+200degC] is obtained when the bulk is connected to the ground. The output voltage variation for a supply voltage sweep between 0.9 V and 1.25 V is 8.6 mV.

A Sub 1V CMOS LNA dedicated to 802.11b/g applications with self-test & high reliability capabilities

A low noise amplifier designed in a 0.13 mum CMOS technology, which has self-test and high reliability capabilities, is presented. Such a LNA could be used in the design of front-end of critical nodes in wireless local area networks to ensure the data transmission. The test of the LNA is based on a built-in self test methodology that permits to monitor its behavior and its reliability is ensured by the use of redundancies. The LNA works under a 0.9 V supply voltage and the test chip has characteristics suitable for 802.11 b/g applications. Parametric faults are injected and detected that demonstrate the efficiency of the BIST circuitry. Switching on each redundant block has proven that the LNA keeps its performances.

A RF circuit design methodology dedicated to critical applications

This paper presents a reliable design methodology dedicated to radio frequency integrated circuits. This methodology is based on common mask design techniques to avoid CMOS failure and on a cold standby redundancy that permits fault tolerance. The methodology has been applied to a low noise amplifier (LNA) demonstrator dedicated to ZigBee applications. The test chip has been realized in a 0.13 mum CMOS VLSI technology. The LNA provides a measured power gain of 12 clBm and a 3.6 dB noise figure, while consuming only 4 mW under a 1.2 V power supply. Measurements on the test chip demonstrate that the addition of the blocks, which achieve the reliable methodology, have no impact on the LNA performances while being efficient.