Seetharaman Sridhar

Shallow trench isolation for advanced ULSI CMOS technologies

This paper reviews the requirements and challenges in designing a Shallow Trench Isolation (STI) process flow for 0.1 /spl mu/m CMOS technologies. Various processing techniques are described for the steps in the STI flow viz. trench definition, corner rounding, gapfill, planarization and well implants. The current capability and scaling requirements for each process step, discussed in the paper, are as follows: (a) Trenches have sidewall angle >/spl sim/80/spl deg/ to maintain trench depth and isolation at narrow space. The trench bottom is rounded to minimize stress. (b) Pad oxide undercut, prior to liner oxidation in halogen ambient or at high temperature, provides adequate corner rounding to suppress edge leakage, with minimum loss of active area. (c) HDP and TEOS-O/sub 3/ CVD oxides can fill 0.16 /spl mu/m wide trenches free of voids. Lower trench aspect ratios (thinner nitride and liner oxide, and shallower trenches), and process improvements allow scaling to smaller dimensions. Gapfill process, liner oxide, and thermal cycles are tailored to prevent stress-induced defects, trench sidewall and corner damage. (d) CMP step height uniformity is improved by using dummy active areas, nitride overlayer or patterned etchback. (e) Optimization of retrograde well and channel stop implants minimizes sensitivity of N/sup +/-P/sup +/ isolation to overlay tolerance and improves latch-up performance.

RF CMOS on high-resistivity substrates for system-on-chip applications

The use of a high-resistivity substrate extends the capability of standard digital CMOS technology to enable the integration of high-performance RF passive components. The impact of substrate resistivity on the key components of RF CMOS for system-on-chip (SoC) applications is discussed. The comparison includes the transistor, transmission line, inductor, capacitor and varactor, as well as the noise isolation. We also discuss the integration issues including latch-up and well-well isolation in a 0.35-/spl mu/m Cu metal pitch, 0.1-/spl mu/m-gate-length RF CMOS technology.

0.1 /spl mu/m RFCMOS on high resistivity substrates for system on chip (SOC) applications

This paper describes the impact of substrate resistivity on the key components of the radio frequency (RF) CMOS for the system on chip (SOC) applications. The comparison includes the transistor, inductor, capacitor, noise isolation, latch-up as well as the well-to-well isolation in a 0.1 /spl mu/m (physical gate length) CMOS technology.

Analog integration in a 0.35 /spl mu/m Cu metal pitch, 0.1 /spl mu/m gate length, low-power digital CMOS technology

This paper describes the integration of active and passive components to enable embedding analog circuits in an advanced digital CMOS technology developed for low standby power integrated circuits. Device design issues, device characteristics, and technology scaling are discussed in this context. The components include 1.5 V digital core CMOS, 1.5 V analog and 3.3 V I/O MOSFETs. In addition to these self-aligned MOSFETs we describe drain-extended transistors, DEnMOS and DEpMOS, where the drain extensions are formed using the well implants. A novel structure to improve the substrate collector, vertical pnp bipolar transistor is presented. The passive components described here are the n-poly on n-well capacitors and a polysilicon resistor with a low temperature coefficient of resistance, usually referred to as the zero-TCR resistor. The analog integration adds one extra mask used to block silicidation of the zero-TCR polysilicon resistor.

Trench isolation step-induced (TRISI) narrow width effect on MOSFET

We report a new narrow-width effect that manifests as an increase in threshold voltage V/sub th/ and in its standard deviation /spl sigma//sub Vth/ as the width W of a MOSFET is reduced to be comparable to the trench isolation step height and the gate polysilicon thickness. At such small W the conformal deposition of polysilicon across the step between the active and isolation regions induces the polysilicon gate to be thicker over the active region. This increased thickness is shown to increase the poly depletion effect causing V/sub th/ shift, a higher /spl sigma//sub Vth/, and higher Vth mismatch. Thus, attention to this detrimental trench isolation step-induced (TRISI) narrow width effect is essential for scaled isolation design.

The effect of deterministic spatial variations in retrograde well implants on shallow trench isolation for sub-0.18 /spl mu/m CMOS technology

The high energy retrograde well implants for sub-0.18 microns CMOS are done at a normal or near normal incidence to minimize the shadowing due to the thick photoresist edges. The endstation geometry in a high energy implanter results in an incident angle variation across the wafer, which causes strong spatial variations in the well profile and can negatively impact device performance. We show that the spatial variations can have significant impact on shallow trench isolation (STI), by causing in a deterministic pattern the failure of STI devices on a wafer. These spatial variations are important and need to be taken into consideration for STI design.

GIDL simulation and optimization for 0.13 /spl mu/m/1.5 V low power CMOS transistor design

In this work, we calibrate a BTBT model based on measured GIDL data, and incorporate the model into our process/device simulations to directly correlate process with device performance and leakage. For the first time, we quantitatively explore an overall picture of tradeoffs between device leakage and performance as functions of process conditions. The explored design space has been used in process optimization for our 0.13 /spl mu/m/1.5 V low power (LP) CMOS transistors. We demonstrate that such predictive TCAD simulations to determine and optimize process conditions can effectively reduce development time and cost. We describe GIDL mechanisms in our 0.13 /spl mu/m/1.5 V LP transistors, and explain, via simulations, that the measured GIDL current manifests different IN behaviors depending on whether the dominant BTBT location is at the gate oxide/Si interface or below in the Si bulk.

Correction to "Trench Isolation Step-Induced (TRISI) Narrow Width Effect on MOSFET"

In the above-named work, an incorrect version of Figs. 1 and 2 appeared. The corrected figures are presented.

Prediction of deep submicron CMOS transistor performance and comparison with projected performance trends using tuned simulations

In this paper, a simulation study to predict the performance of CMOS technology in the deep sub-micron regime (0.20 micrometer down to 0.05 micrometer) is presented. The metric used to evaluate the CMOS transistor performance is a Figure of Merit (FOM). Using tuned process and device simulators, the performance FOM of bulk CMOS technologies were evaluated, with varying (1) gate lengths in the range of 0.05 - 0.20 micrometer, (2) power supply voltages (Vdd) of 1.0 - 1.8 V, (3) gate oxide thicknesses (Tox) of 20 - 40 A, (4) maximum off-state leakage currents of 0.01, 1 and 100 nA/micrometer, (5) different source/drain resistances and (6) different polysilicon doping levels. Vdd and Tox were scaled with gate length such that Vdd/Tox is fixed at about 5 MV/cm. It is found that it is increasingly difficult to keep the proportionality between performance FOM and 1/Lgate as the gate length is scaled to around 0.10 micrometer or below. This deviation is due to the decreasing trend of transistor drive current caused by the low supply voltages to be used and the nonscalability of VT. In order to try and improve the performance of CMOS technology, metal-gated Fully Depleted SOI CMOS transistors were evaluated in this study. It was found that although Fully Depleted Metal-Gate SOI provides an improvement in performance over conventional bulk CMOS technology, the FOM does not linearly scale with the gate length. The improvement in FOM obtained is almost entirely due to the smaller junction capacitance in SOI and not due to significantly increased drive currents in metal-gate FD-SOI when compared to conventional CMOS. Further, FOM performance falls short of the roadmap targets as the gate lengths are scaled below 0.10 micrometer just as in bulk CMOS. The effects of Off Current specifications and supply voltage on FOM were studied. It is shown that the CMOS performance can be improved by: (1) slightly increasing the supply voltage, and (2) using a dual- VT approach in which low-VT transistors are used in the critical path to improve circuit performance. With these approaches it is possible to extend the proportionality between FOM and 1/Lgate down to about 0.08 micrometer gate length.

The effect of deterministic spatial variations in retrograde well implants on shallow trench isolation and latchup immunity

The retrograde well implants for sub-0.18 /spl mu/m CMOS are done at a normal or near-normal incidence to minimize shadowing due to the thick photoresist edges. The endstation geometry in the high energy implanter results in an incident angle variation across the wafer, which causes strong spatial variations in the well profile and can negatively affect device performance. We show that the spatial variations can have significant impact on shallow trench isolation (STI), latchup immunity, well resistance and capacitance. The spatial variations can cause in a deterministic way the failure of a large number of isolation structures on a single wafer.