Manabu Takakuwa

Patterning performance of hyper NA immersion lithography for 32nm node logic process

We have developed the lithography process for 32nm node logic devices under the 1.35NA single-exposure conditions. In low-k1 generation, we have to consider the minimum pitch resolution and two-dimensional pattern fidelity at the same time. Although strong RET (Resonance Enhancement Technique) can achieve the high image contrast, it has negative effects like line end shortening and resist pattern collapse. Moderate RET such as annular illumination can combine the minimum pitch resolution and two-dimensional pattern fidelity with hyper NA illumination condition. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 110nm for contact hole pattern, respectively. The isolated contact hole needs SRAF and focus drift exposure to improve DOF. Embedded SRAM cell of 0.125&mgr;m2 area is clearly resolved across exposure and focus window.

Mix-and-match overlay method by compensating dynamic scan distortion error

This paper discusses the compensation method and APC system to reduce errors in mix and matching overlay between scanners. We proposed the compensation model for intra-field errors in mix and matching. And we developed the advanced APC system also to improve dynamic scan distortion using the compensation model.

Overlay sampling optimization by operating characteristic curves empirically estimated

Operating Characteristic (OC) curves, which are probabilities of lot acceptance as a function of fraction defective p, are powerful tools for visualizing risks of lot acceptance errors. The authors have used OC curves for the overlay sampling optimization, and found that there are some differences in probability of acceptance between theoretical calculation and empirical estimation. In this paper, we derive a theoretical formulation of the probability of acceptance for several simple cases by decomposing overlay errors, and show that the origin of the differences is the use of stratified sampling in overlay inspection.

Feasibility of Ultra-Low k1 Lithography for 28nm CMOS Node

We have designed the lithography process for 28nm node logic devices using 1.35NA scanner. In the 28nm node, we face on the ultra-low k1 lithography in which dense pattern is affected by the mask topography effect and the oblique-incidence. Using the rigorous lithography simulation considering the electro-magnetic field, we have estimated accurately the feasibility of resolution of the minimum pitch required in 28nm node. The optimum mask plate and illumination conditions have been decided by simulation. The experimental results for 28nm node show that the minimum pitch patterns and minimum SRAM cell are clearly resolved by single exposure.

Aberration Monitoring toward Wavefront Matching with Device Patterns

Wavefront matching is a new technique for compensating uncontrollable aberration effects on a certain reticle design which involves moving controllable aberrations. Such a compensation concept is crucial for producing system-on-chip devices using photolithography. A high-precision wavefront monitor is an essential item for the wavefront matching. The resist-based aberration measurement technique based on the three-beam interference theory is a candidate for monitoring. In the present work, the wavefront in the lithography lens was driven by the lens controller, and then the slight change from the initial state was measured using the technique. For the experiment, a krypton fluoride excimer laser scanner with a numerical aperture (NA) of 0.68 was used. The measurement results verified that the technique has sufficient sensitivity to monitor the wavefront matching.