Kazutaka Ishigo

Alignment mark signal simulation system for the optimum mark feature selection

Recently, requirements concerning overlay accuracy have become much more restrictive. For the accurate overlay, signal intensity and wave form from the topographical alignment mark have been examined by signal simulation. However, even if the results were in good agreement with actual signal profiles, it would be difficult to select particular alignment marks at each mask level by the signal simulation. Therefore, many mark candidates are left in the kerf area after mass production. To facilitate the selection, we propose a mark TCAD system. It is a useful system for the mark selection with the signal simulation performed in advance. In our system, the alignment mark signal can be easily simulated after input of some process material parameters and process of record (POR). The POR is read into the system and a process simulator makes stacked films on a wafer. Topographical marks are simulated from the stacked films and the resist pattern. The topographical marks are illuminated and reflected beams are produced. Imaging of the reflected beams through inspection optics is simulated. In addition, we show two applications. This system is not only for predicting and showing a signal wave form, but is also helpful for finding the optimum marks.

Patterning strategy and performance of 1.3NA tool for 32nm node lithography

We have designed the lithography process for 32nm node logic devices under the 1.3NA single exposure conditions. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 120nm for contact hole pattern, respectively. The isolated feature needs SRAF to pull up the DOF margin. High density SRAM cell with 0.15um2 area is clearly resolved across exposure and focus window. The 1.3NA scanner has sufficient focus and overlay stability. There is no immersion induced defects.

Integration of a new alignment sensor for advanced technology nodes

In this paper alignment and overlay results of the advanced technology nodes are presented. These results were obtained on specially generated wafers as well as on regular manufacturing-type wafers. For this purpose, a new alignment sensor was integrated and evaluated in three generations of lithography tools, placed in R&D and mass manufacturing facilities. The capability of the sensor to align on marks with varying layout was evaluated. Long term overlay stability less than 11 nm was obtained on two different mark types: a standard ASML calibration mark and a flexible Toshiba mark design. The ability to align on low-contrast marks was validated by a dedicated experiment: typical alignment repeatability values of ~1 nm (3sigma) on shallow etch depth mark features of 25 nm are obtained for various mark designs, including flexible pitch alignment marks. From these results, design directions for improved mark detect ability were defined. The jointly developed mark designs were validated for their alignment robustness by an evaluation of manufacturing wafer alignment performance. On-product overlay results on manufacturing wafers were measured for three different process layers of the current technology node. The used alignment strategies were based on new mark capture and fine wafer alignment mark designs, thereby making optimal use of the mark design flexibility potential of the alignment sensor. Typical on-product overlay values obtained were less than 17 nm for the Active Area process layer, less than 12 nm for the Gate Conductor process layer, and less than 19 nm for the Metal-1 process layer; after applying batch corrections, as determined on a set of 2 send-ahead wafers. All results are based on full batch readout on an offline metrology tool. By applying optimal batch process corrections for linear terms, typical overlay values range between 10-14 nm, depending on the layer measured. Finally the sensors infrared wavelengths were used to demonstrate a robust alignment solution for wafers containing a semi-transparent hard-mask layer.

Mask image position correction for double patterning lithography

Application of double patterning technique has been discussed for lithography of HP 3X nm device generation. In this case, overlay budget for lithography becomes so hard that it is difficult to achieve it with only improvement of photomasks position accuracy. One of the factors of overlay error will be induced by distortion of photomask after chucking on the mask stage of exposure tool, because photomasks are bended by the force of vacuum chucking. Recently, mask flatness prediction technique was developed. This technique is simulating the surface shape of mask when it is on the mask stage by using the flatness data of free-standing state blank and the information of mask chucking stage. To use this predicted flatness data, it is possible to predict a pattern position error after exposed and it is possible to correct it on the photomask. A blank supplier developed the flatness data transfer system to mask vender. Every blanks are distinguished individually by 2D barcode mark on blank which including serial number. The flatness data of each blank is linked with this serial number, and mask vender can use this serial number as a key code to mask flatness data. We developed mask image position correction system by using 2D barcode mark linked to predicted flatness data, and position accuracy assurance system for these masks. And with these systems, we made some masks actually.

Flexible alignment mark design applications using a next generation phase grating alignment system

In this paper, alignment and overlay results on processed short-flow wafers are presented. The impact of various mark designs on overlay performance was investigated, using a newly developed phase grating wafer alignment sensor concept. This concept is especially suited to support mark design flexibility, as well as to further improve upon the performance of the alignment sensors currently known. The unique sensor concept allows for alignment to a large variety of marks layouts, thereby complying with customer specific alignment mark design requirements. Here, we present alignment performance results on Toshibas new marks. For this purpose, the new alignment sensor was integrated in an ASML proto-type tool. Alignment performance on ASML default mark types was demonstrated to guarantee backward compatibility with known alignment sensors. Alignment repeatability numbers of <3 nm (3sigma) were obtained for the different mark designs investigated. These numbers were measured on marks in resist as well as on processed short flow lots. Short term overlay capability of <6 nm (mean+3sigma) was demonstrated on Toshiba mark types, and on ASML mark types. Long term overlay values were demonstrated to be below 8 nm (mean + 3sigma) for both mark designs. The alignment and overlay capability, on processed wafers, was demonstrated for two process modules: Gate-to-Active (GC-AA) and Metal1-to-Contact (M1-CS). Typical overlay values measured were 20 to 30 nm, for the GC-AA and the M1-CS process module respectively. Further improvements with respect to alignment performance and overlay capability are anticipated through the use of advanced applications, and by further optimization of alignment mark design. This will be verified in future joint Toshiba/ASML experiments.

Overlay sampling optimization by operating characteristic curves empirically estimated

Operating Characteristic (OC) curves, which are probabilities of lot acceptance as a function of fraction defective p, are powerful tools for visualizing risks of lot acceptance errors. The authors have used OC curves for the overlay sampling optimization, and found that there are some differences in probability of acceptance between theoretical calculation and empirical estimation. In this paper, we derive a theoretical formulation of the probability of acceptance for several simple cases by decomposing overlay errors, and show that the origin of the differences is the use of stratified sampling in overlay inspection.

Impact of patterning strategy on mask fabrication beyond 32nm

Mask specifications of the pitch splitting type double patterning for 22nm node and beyond in logic devices have been discussed. The influences of the mask CD error and the mask induced overlay error on wafer CD have been investigated in both cases of bright field and dark filed. The specification for intra-layer overlay alignment is much smaller than inter-layer one. The specification of mask CD uniformity for dark is more challenging. In order to overcome the technology gap between single patterning and double patterning, many things will have to be improved.

Double Gate MOSFET by ESS (Empty Space in Silicon) Architecture

Double gate (DG) MOSFET employing ESS (Empty Space in Silicon) architecture exhibited remarkable device characteristics. Significant performance gain was clearly observed comparing to a planer bulk device. This advantage is mainly due to the steep sub-threshold characteristic which is the typical double gate feature. The ESS double gate architecture is fully compatible with current conventional bulk CMOS process. This typical feature could make double gate FET into realistic candidate of next high performance device. Introduction FD/DG/GAA-SOI has been discussed as a promising structure for future scaling devices because of the high SCE and DIBL immunity. However, complicated integration scheme will be needed to realize such kind of devices. On the other hand, we had developed the new technique to fabricate SON (Silicon on Nothing) structure on bulk substrate, named ESS technique. The ESS technique has several advantages; (1) Partial SOI (SON) on bulk substrate: The merit of SOI structure can be utilized on bulk wafer. This is appropriate for System on a Chip (SoC) applications. (2) Simple process: The ESS process needs only the trench fabrication and high temperature annealing. This will produce significant process cost reduction comparing to the use of SOI wafer. (3) Low self-heating: The ESS structure is made at part of active area region. Thus, thermal flux can easily flow into the Si substrate. (4) Free layout: ESS with the arbitrary size and shape can be formed by controlling the initial trench size and layout. In this paper, distinguished DG FET characteristics will be demonstrated with practical ESS architecture. DG-ESS FET Process A simple process sequence of the DG-ESS FET is shown in Fig. 1. First, high aspect ratio trenches were formed at surface of Si wafer. After that, ESS was formed by the trench transformation on high temperature hydrogen annealing. Next, SON thickness was thinned by CMP and oxidation process. Then, flat device surface over the ESS was obtained. STI pattern was aligned with ESS pattern. Conventional CMOS process could be applied after STI process. In this study , HDP-USG (anisotropic deposition property) was used for filling the STI. Thus, the ESS was not filled at STI formation step and a seam was created beside the ESS. As a result, the ESS was filled by polysilicon as a bottom gate electrode at the same time of top gate electrode deposition. The surrounding gate structure was made with this buried polysilicon. Figure 2 shows the schematic layout of the DG-ESS FET. Pipe-shaped ESS is formed under the top gate and extends to the STI region. Figures 3 and 4 show the TEM image of the A-A’ and B-B’ cross section of the fabricated DG-ESS FET, respectively. No defect was observed at the channel region and around ESS structure. Also it was confirmed that the thin flat Si layer surrounded by the poly silicon gate could successfully be obtained. In this structure, there is no need to make a contact to bottom gate electrode. The bottom surface of active Si layer was atomically flat due to surface migration. Thus, thickness of active Si layer became quite uniform as can be seen in fig. 4. Device Characteristics and Discussions Electrical results of DG-ESS FET were verified comparing to conventional bulk MOSFET, which were fabricated on the same wafer. The size of ESS and the thickness of the active Si layer should be well controlled to enjoy the merits of DG structure. Figure 5 shows the dependence of threshold voltage on substrate voltage at several gate lengths. The body effect coefficient of DG-ESS FET is varying with the change of gate length for a given ESS size. At the short channel region, where the gate length is shorter than the size of ESS, channel region is electrically isolated from the substrate. This device is same as floating body double gate structure. Figure 6 shows ideal subthreshold property at the shortest gate length which is around 0.2μm. On the other hand, in case that gate length is 1.0μm, which is larger than the ESS size, there is no difference in device characteristics at all regardless of ESS. As shown in Figs. 5 and 6, gate length has to be set shorter than ESS size to obtain the merit of floating body double gate device. Typical Id-Vg and Id-Vd characteristics of DG-ESS FET are shown in figs. 7 and 8, respectively. Steep subthreshold characteristics and higher drive current were observed. Drain current enhancement of DG-ESS FET was successfully achieved by 75% for NMOS and 97% for PMOS comparing to bulk FET which has same device width. On the other hand, the series resistance in the extension region could become important when the gate length becomes much shorter than the ESS size. However, the size of ESS is well controllable for each gate length. Finally, self-heating effect, which is one of critical issues of SOI device, was simulated using SON FET structure. The lattice temperature distribution due to self-heating was simulated as shown in Fig. 9 for conventional SOI FET(left) and SON FET(right). The better heat dissipation was clearly confirmed on SON FET since there is no insulator under source and drain region. DG-ESS FET shows more better heat dissipation than SON FET because SON region is filled with silicon, which has 100x lower thermal resistance compare to buried oxide. Conclusions DG-ESS FET was successfully realized by using ESS technique. DG-ESS FET shows the high drivability and good subthreshold property. Simple process sequence for making DG device has been demonstrated, which is compatible with conventional CMOS process. As a result, this novel scheme can fabricate both double gate and conventional device on the same wafer without any performance degradation. These results suggest that DG devices using ESS architecture is appropriate for SoC applications, due to the merit that DG structure can be fabricated partially on bulk substrate. References 1) J. P. Colinge et al., SSDM Tech. Dig., p.238, 2001. 2) D. Hisamoto, IEDM Tech. Dig., p.429, 2001. 3) S. Monfray et al., VLSI Tech. Dig., p.108, 2002. 4) T. Sato et al., IEDM Tech. Dig., p.517, 1999. 5) I. Mizushima et al., Appl. Phys. Lett., 77, p.3290, 2000. 6) T. Sato et al., IEDM Tech. Dig., p.809, 2001. Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials, Tokyo, 2003, 762 B-10-6L pp. 762-763