Manabu Tomisaka

High-Aspect-Ratio Copper Via Filling Used for Three-Dimensional Chip Stacking

Through-chip electrodes for three-dimensional packaging can offer short interconnection and reduced signal delay. Formation of suitable vias by electrodeposition into cavities presents a filling problem similar to that encountered in the damascene process. Because via dimensions for through-chip filling are larger and have a higher aspect ratio relative to features in damascene, process optimization requires modification of existing superconformal plating baths and plating parameters. In this study, copper filling of high-aspect-ratio through-chip vias was investigated and optimized with respect to plating bath composition and applied current wavetrain. Void-free vias 70 mu m deep and 10 mu m wide were formed in 60 min using additives in combination with pulse-reverse current and dissolved-oxygen enrichment. The effects of reverse current and dissolved oxygen on the performance of superfilling additives is discussed in terms of their effects on formation, destruction, and distribution of a Cu(I) thiolate accelerant. (c) 2005 The Electrochemical Society. All rights reserved.

Thermal characterization of bare-die stacked modules with Cu through-vias

This paper describes the thermal characteristics of three dimensional (3-D) modules where four bare-dies with Cu through-vias are vertically stacked and electrically connected through the Cu-vias and the metal bumps. To realize more accurate thermal analysis for the 3D-modules in the earlier stage of the process development, a series of simple thermal resistance measurements by laser-flash method and parametric numerical analyses have been carried out. First, the thermal effects of the interface between two layers were quantified on the basis of the results of the laser-flash method. Second, using experimental interfacial thermal resistance, the thermal conduction analyses for 3D-modules were carried out. The key parameters governing the thermal performance of bare-die stacked modules and the design guideline of the thermal bumps are presented.

Development of wafer thinning and double-sided bumping technologies for the three-dimensional stacked LSI

The three-dimensional (3D) chip stacking technology has been developed extensively recently for the next generation packaging technology. The technology includes thorough electrode fabrication, wafer thinning, wafer backside processing, testing, and chip stacking. Wafer thinning and wafer backside processing are important technologies among them, because these technologies accommodate small and thin form factor, enable thin chip stacking, and enhances electrical and mechanical reliability of the stacked module. In this paper, novel technologies of wafer thinning and wafer backside processes that include insulation film formation and bumping on the backside of the thinned wafer are described.

Copper Electrodeposition of High-Aspect-Ratio Vias for Three Dimensional Packaging

Through chip electrodes with high aspect ratios offer the shortest interconnection and reduce signal delay. In this work, filling vias with higher aspect ratio copper, 10 μm in square and 70 μm in depth, used for through chip electrodes was investigated, using a commercially-available bath and a specially-designed one. We used the commercially-available bath containing CuSO 4 .5H 2 O and H 2 SO 4 for basic bath, and PEG (polyethylene glycol), JGB (Janus Green B), SPS (Bis (3-sulfopropyl) disulfide) and HCl as additives. With this commercially-available bath of optimized composition, electroplating time was shortened to 3.5 hr by adopting two-step electroplating method, i.e. application of initial lower current density level of 2 mA/cm 2 for 2 hr and final higher current density level of 3 mA/cm 2 for 1.5 hr. Furthermore, electroplating time of 2.5 hr was achieved with the use of specially-designed bath: (SPS, SPR B, LEV A) = ( 2 ppm, 2 ppm, 0.5 ppm).

Electroplating Cu Filling Study for Thorough Electrode in Silicon Wafer of Three Dimensional LSI Chip Stacking

l.Introduction Recently three-dimensional (3D) I,SI stacking technologies with through electrode are studied extensively [1-5]. It will rcalize high-density packaging and high operation performance. It offers shortest interconnection between chips to reduce signal delay. In this paper, we studied via tilling for through electrode in silicon wafer. It will be used for three-dimensional LSI chip stacking. The dependence of via filling on via top shape and electroplating conditions were studied. We found that vias L0 pm square and 70 pm depth could be almost filled up by conventional solution and equipment for LSI interconnection. Because of the difficulty to maintain adequate concentration of additives [6] during production, we investigted simple solution that only brightener was added with a new technology for agitation (supervibratory method) to fill the vias.