Santhosh Onkaraiah

Bipolar ReRAM Based non-volatile flip-flops for low-power architectures

Resistive Random Access Memories (ReRAMs) fabricated in the back-end-of-line are a promising breakthrough for including permanent retention mechanisms in embedded systems. This low-cost solution opens the way to advanced power management schemes. In this paper, we propose novel design architecture of a non-volatile flip-flop based on Bipolar ReRAMs (Bi-RNVFF). Compared to state-of-the-art Data-Retention flip-flop (with Balloon latch), the proposed design is 25% smaller due to 6T structure compared to the 8T structure of Data-Retention flip-flop. Moreover, being non-volatile, the proposed architecture exhibits a zero leakage compared to a Data-Retention Flip-Flop, which consumes ~3.2μW in sleep mode (leakage) for a 10K Flip-Flop design implemented in 22nm FDSOI technology. Our simulation results show that Bi-RNVFF is a true alternative for future “Power-on, Power-off” application adding Non-Volatility without significant burdening of the existing architectures.

Using OxRRAM memories for improving communications of reconfigurable FPGA architectures

New memories, such as non-volatile resistive memories present bright prospect in catering to the ever-growing memory needs. In this paper, we investigate the usage of Oxide Resistive Random Access Memory (OxRRAM) to improve the communication switchboxes of Field-Programmable-Gate-Arrays (FPGAs). We prove the interest of using unipolar OxRRAM in such devices thanks to a complete methodology, starting from compact model based on self-consistent physical model up to architectural evaluation using typical FPGA benchmarks. Besides, the architectural gains in terms of area by 1.4x and write time by 17.4x in comparison with phase-change memories (PCM). An improvement in area by 4.82x and write time by 285.7x for conventional Flash technology as well as a reduction in overall delay by 49.3% due to the reduced on-resistance and smaller size are reported.

Resistive memories: Which applications?

Recent announcement of 16Gbits Resistive memory from Sony shows the trend to quickly adopt resistive memories as an alternative to DRAM. However, using ReRAM for embedded computing is still a futuristic goal. This paper approaches two applications based on ReRAM-devices for gaining area, performance or power consumption. The first application is FPGA, one of the first architecture that can benefit the most from ReRAM integration to reduce footprint and save energy. The second application relates to ultra-low-power systems and the way to obtain an instantaneous “freeze” mode in devices for Internet of Things.

Interface Engineering of Ag-

In this paper, we show performance and reliability improvement of Ag- GeS2-based conductive bridge RAM (CBRAM) devices by addition of a 2-nm-thick HfO2 layer between the electrolyte and the W bottom electrode. Our optimized dual-layer electrolyte stack (2-nm HfO2-30-nm GeS2) leads to a resistance ratio (ROFF/RON) higher than 106 and projected 10 years read disturb immunity at 0.04 V. The improved memory resistance ratio is explained by means of physical modeling. Using compact modeling and circuit level simulations, we show that our optimized CBRAM device, integrated in a 1T-2R architecture, fits well with the aggressive requirements of field programmable gate array-type reconfigurable applications. Nonvolatility, back-end-of-line compatibility, and 1.3-nA leakage current during continuous reverse read operation at 1 V are strong benefits demonstrated on our device for such applications.

{\rm GeS}_{2}

Abstract “Normally Off, Instantly On” applications are becoming common in our environment. They range from healthcare to video surveillance. As the number of applications and their associated performance requirements grow rapidly, more and more powerful, flexible, and power efficient computing units are necessary. In such a context, Field Programmable Gate Arrays (FPGA) architectures present a good trade-off between performance and flexibility. However, they consume high static power and can hardly be associated with power-gating techniques due to their long context-restoring phase. In this paper, we propose to integrate non-volatile resistive memories in the configuration cells and registers in order to instantly restore the FPGA context. If the circuit is in the ‘ON’ state for less than 42% of time, non-volatile FPGA starts saving energy compared to classical FPGA. Finally, when context-saving functionality is included, for a typical application with only 1% of time spent in the ‘ON’ state, the energy gain exceeds 40%.

-Based Conductive Bridge RAM for Reconfigurable Logic Applications

This paper presents a 2-to-2 interconnect switch based on Conductive Bridging Random Access Memories (CBRAMs), which can be used to form a switch box in reconfigurable logic circuits like FPGAs. Interconnect switching as well as configuration storage are achieved by the same resistive switching devices. The solution is stable without read disturb and false programming, and brings an area saving of more than two, compared to the current SRAM based circuits. It is a promising breakthrough for including permanent retention mechanisms in embedded systems at low cost.

RRAM-based FPGA for “Normally Off, Instantly On” applications

At most advanced technology nodes, Field Programmable Gate Arrays (FPGA) present great advantages compared to more conventional processor architectures; their natural regularity, modularity and inherent reliability due to duplicated identical tiles provide a solution to overcome new technologies with increasing variability. However, FPGA market is still limited by power efficiency issue, due to two coordinated factors like interconnection-dominated design and large usage of memories, computation being performed thanks to Look-Up-Table (LUT). In this paper, we propose a solution to improve the performance and reduce the power consumption of LUT in FPGA using CBRAM-based structures. Our proposed design shows significant improvement compared to the traditional SRAM-based FPGA in: critical delay is reduced by ~23% due to compact structure (1T-2R) and power gain by reduction in static power consumption by ~18%.

A CBRAM-based compact interconnect switch for non-volatile reconfigurable logic circuits

This paper gives an overview of our research work on Oxide Resistive switching memory (OxRAM) at technology and design level. The OxRAM technology has been developed in order to be co-integrated with low-voltage advanced CMOS technologies. The device electrical characteristics show: (i) a switching time of 100ns at 1V, (ii) an excellent data retention at 150°C and (iii) a high endurance up to 108 cycles. The second part of this paper focuses on circuit design. The benefits of 3D integration of non-volatile devices on CMOS are highlighted. Performance and area gains are discussed as well as new application features.

A hybrid CBRAM/CMOS Look-Up-Table structure for improving performance efficiency of Field-Programmable-Gate-Array

In this paper, we propose a novel HfO2-GeS2-Ag based Conductive Bridge RAM (CBRAM) device as a promising candidate to replace Flash and SRAM-based configuration memory in reconfigurable logic circuits, such as Field Programmable Gate Arrays (FPGAs). In order to evaluate the feasibility of our new cell for FPGA architectures, 1T-1R CBRAM devices (both isolated and 8×8 matrix) were electrically characterized in a range of logic compatible programming conditions. A resistance ratio (Roff/Ron) of 106 between off/on states, small programming currents (lower than 100 μA) and projected 10 years disturb immunity at 0.04 V are demonstrated. We argue that the optimized cell, integrated in a 1T-2R CBRAM architecture, fits well with the aggressive requirements of a configuration memory because of being non volatile, Back-End-Of-Line (BEOL) compatible and exhibiting sub-200 pA leakage current during read operation.

Back-end 3D integration of HfO 2 -based RRAMs for low-voltage advanced IC digital design

Emerging nonvolatile memories (NVM) based on resistive switching mechanism such as RRAM are under intense R&D investigation by both academics and industries. They provide high write/read speed, low power, and good endurance (e.g., >1012) beyond mainstream NVMs, enabling them to be a good candidate for Flash replacement in microcontroller unit. This replacement could significantly decrease the power consumption and the integration cost on advanced CMOS nodes. This paper presents first the HfO2-based RRAM technology and the associated compact model, which includes related physics and model card fitting experimental electrical characterizations. The 128 kb memory architecture based on RRAM technology and 28 nm fully depleted silicon on insulator (FDSOI) CMOS core process is presented with a bottom-up approach, starting from the bit-cell definition up to the complete memory architecture implementation. The key points of the architecture are the use of standard logic MOS exclusively, avoiding any high voltage MOS usage, program/verify procedure to mitigate cycle to cycle variability issue and direct bit-cell read access for characterization purpose. The proposed architecture is validated using postlayout simulations on MOS and RRAM corner cases.