Mathieu Moreau

Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories

Emerging non-volatile memories (NVM) based on resistive switching mechanism (RS) such as STT-MRAM, OxRRAM and CBRAM etc., are under intense R&D investigation by both academics and industries. They provide high write/read speed, low power and good endurance (e.g., > 1012) beyond mainstream NVMs, which allow them to be embedded directly with logic units for computing purpose. This integration could increase significantly the power/die area efficiency, and then overcome definitively the power/speed bottlenecks of modern VLSIs. This paper presents firstly a theoretical investigation of synchronous NV logic gates based on RS memories (RS-NVL). Special design techniques and strategies are proposed to optimize the structure according to different resistive characteristics of NVMs. To validate this study, we simulated a non-volatile full-adder (NVFA) with two types of NVMs: STT-MRAM and OxRRAM by using CMOS 40 nm design kit and compact models, which includes related physics and experimental parameters. They show interesting power, speed and area gain compared with synchronized CMOS FA while keeping good reliability.

Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells

Abstract Emerging non-volatile memories (e.g. STT-MRAM, OxRRAM and CBRAM) based on resistive switching are under intense research and development investigation by both academics and industries. They provide high performance such as fast write/read speed, low power and good endurance (e.g. >1012), and could be used as both computing and storage memories beyond flash memories. However the conventional access architecture based on 1 transistorxa0+xa01 memory cell limits its storage density as the selection transistor should be large enough to ensure enough current for the switching operation. This paper presents the design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells with a particular focus on reliability and power performance investigation. This architecture allows fewer selection transistors, and minimum contacts between memory cells and CMOS control circuits. The complementary cell and parallel data sensing mitigate the impact of sneak currents in the crossbar architecture and provide fast data access for computing purpose. We perform transient and statistical simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the functionality of this design by using CMOS 40 nm design kit and memory compact models, which were developed based on relative physics and experimental parameters.

SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures

Passive crossbar memories based on resistive switching bit-cells are today seen as the most promising candidates for flash memories replacement. However, inherent sneak currents through unselected devices lead to low operating margins and over-consumption during read and programming operations. Crossbar memory simulations with bit-cells based on two terminal nonlinear selectors, also show degraded performances due to sneak path currents, leading to nonfunctional memories. Thus, peripheral circuits have to be designed in order to mitigate the sneak currents that impact memory operations. In this paper, we propose a dynamic sneak current compensation circuit for SET and read operations, enabling multi-level cell programming. This circuit is simulated using CMOS 130nm Bulk core process with OxRAM and tunnel barrier-based selector bit-cell.

A novel test structure for OxRRAM process variability evaluation

Common problems with resistive Oxide-based Resistive Random Access Memory (so-called OxRRAM) are related to high variability in operating conditions and low yield. Although research has taken steps to resolve these issues, variability remains an important characteristic for OxRRAMs. In this paper, a test structure consisting of non-addressable OxRRAM cells with parallel connection of all memory elements is introduced. The test structure provides useful information regarding OxRRAM variability. The test structure can be used as a powerful tool for process variability monitoring during a new process technology introduction but also for marginal cell populations detection during process maturity.

Synchronous full-adder based on complementary resistive switching memory cells

Emerging non-volatile memories (NVM) such as STT-MRAM and OxRRAM are under intense investigation by both academia and industries. They are based on resistive switching mechanisms and promise advantageous performances in terms of access speed, power consumption and endurance (i.e. >1012), surpassing mainstream flash memories. This paper presents a non-volatile full-adder design based on complementary resistive switching memory cells and validates it through two NVM technologies: STT-MRAM and OxRRAM on 40 nm node. This architecture allows low power consumption. Thanks to the nonvolatility and 3D integration of NVM, both standby power during “idle” state and data transfer power can be reduced. Using a low changing frequency can also control the switching power of NVM. The complementary cells and parallel data sensing enable fast computation and high reliability.

Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures

With the arrival of crosspoint based memories on the consumer market, high-density resistive memories could be introduced as flash memories replacement or as storage class memory. However, transistor-Less Resistive memory architectures using 1Selector-1resistance bitcells suffer from performances loss due to sneaking current through unselected bitcells. Beyond the back end of line selector design, circuit design solutions have to be pushed in order to improve precision during programming steps. In this paper we propose a novel capacitor based 2-steps SneakPath compensation circuit for transistor-less architectures of resistive memories. Compared to standard SneakPath compensation circuits, it ensures up to 20× of area improvement and more than 3× reduction of the variability effects for a 28nm CMOS node.

Analytical study of complementary memristive synchronous logic gates

This paper describes an analytical study of synchronous logic gate design based on hybrid structure with MOS and resistive switching non-volatile memories (RS-NVMs). This type of structure allows ultra-low power consumption during power down, while often-used data are saved in RS-NVM cells. The parallel data sensing achieves low-power and fast computation time. The logic gate construction theory, from Boolean equation to hybrid MOS/RS-NVM tree, is deeply detailed. Read and write design guideline, regarding RS-NVM and MOS resistance balance are investigated. Practical implementation is given through transient simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the concept by using CMOS 40 nm design kit and memory compact models.

Single-ended sense amplifier robustness evaluation for OxRRAM technology

In this paper, impact of OxRRAM cell variability on circuit performances is analyzed quantitatively at a circuit level. A single-ended sense amplifier architecture is evaluated against memory cell variability. This study enables enhancing OxRRAM yield as well as reducing cell consumption during a read operation without compromising reliability. Due to the stochastic nature of the switching process in OxRRAMs, leading to large variability, all simulations are Monte Carlo oriented.

Design and Simulation of a 128 kb Embedded Nonvolatile Memory Based on a Hybrid RRAM (HfO2 )/28 nm FDSOI CMOS Technology

Emerging nonvolatile memories (NVM) based on resistive switching mechanism such as RRAM are under intense R&D investigation by both academics and industries. They provide high write/read speed, low power, and good endurance (e.g., >1012) beyond mainstream NVMs, enabling them to be a good candidate for Flash replacement in microcontroller unit. This replacement could significantly decrease the power consumption and the integration cost on advanced CMOS nodes. This paper presents first the HfO2-based RRAM technology and the associated compact model, which includes related physics and model card fitting experimental electrical characterizations. The 128 kb memory architecture based on RRAM technology and 28 nm fully depleted silicon on insulator (FDSOI) CMOS core process is presented with a bottom-up approach, starting from the bit-cell definition up to the complete memory architecture implementation. The key points of the architecture are the use of standard logic MOS exclusively, avoiding any high voltage MOS usage, program/verify procedure to mitigate cycle to cycle variability issue and direct bit-cell read access for characterization purpose. The proposed architecture is validated using postlayout simulations on MOS and RRAM corner cases.

Oxide based resistive RAM: ON/OFF resistance analysis versus circuit variability

A deeper understanding of the impact of variability on Oxide-based Resistive Random Access Memory (so-called OxRRAM) is needed to propose variability tolerant designs to ensure the robustness of the technology. Although research has taken steps to resolve this issue, variability remains an important characteristic for OxRRAMs. In this paper, impact of variability on OxRRAM circuit performances is analysed quantitatively at a circuit level through electrical simulations. Variability is introduced at the memory cell level but also at the peripheral circuitry level. The aim of this study is to determine the contribution of each component of an OxRRAM circuit on the ON/OFF resistance ratio.