Marie-Claude Paquet

Underfill selection strategy for Pb-free, low-K and fine pitch organic flip chip applications

The role of underfills is expanding from preserving solder joint reliability to also protecting fragile low-k chip dielectric layers. Traditionally, solder joints required stiff and rigid underfills. Today, low-k layers require more compliant underfill properties. Further complexity comes from the migration to Pb-free solders and changes in chip carrier materials. The myriad of candidates prohibits long term reliability testing of module hardware for every available underfill. A sequential three phase selection strategy is used to characterize and systematically eliminate undesirable candidates and to identify the few favorable underfills that have a high probability of successfully meeting module reliability requirements. The process includes use of industry practices as well as internally developed characterization methods. From an initial list of 20, the selection process identified five underfills for package qualification testing

Underfill delamination to chip sidewall in advanced flip chip packages

A number of failure mechanisms related to the underfill material in flip chip plastic ball grid array packages are well documented in the literature (underfill-to-chip passivation delamination, underfill-to-substrate soldermask delamination, chip cracking, interconnect fatigue, etc.). This paper discusses the delamination of the underfill from the chip sidewalls, another failure mechanism which has become more prevalent with component material changes, increases in die dimensions, finer C4 pitches and substrates with larger coefficient of thermal expansion. A detailed study is presented for the initiation of underfill-to-sidewall delamination, based on experimental data as well as finite element modeling. It is shown generally that both stress at the chip-underfill interface near the chip corner, and poor adhesion of the underfill to the chip sidewalls contribute to the initiation of underfill delaminations. Various parameters influencing stress (package design, underfill material thermo-mechanical properties) and adhesion (underfill base chemistry and additives, filler treatment, chip sidewall cleanliness) are discussed.

From Leaded to Lead Free Assembly and New Packaging Technology Challenges

The migration to lead free connections in the microelectronic industry has brought forth many technical challenges, especially in the packaging technology area with respect to materials and processes. The two major drivers to these challenges are the higher melting point and the thermo-mechanical behaviour (less creep than SnPb alloy) of the replacement alloy. The higher melting point drives higher reflow temperatures during the packaging assembly as well as the card assembly and this requires the use of new materials. Higher stresses in the package can result in a reliability impact for the product. The challenge of these lead free related changes is exacerbated by other trends in leading edge organic packaging such as chip low K dielectric materials, larger package and larger chip dimensions and, reduced chip bump pitch. This paper provides the reliability results obtained through various lead free organic package test matrices and qualifications. The principal failure mechanisms are presented and are explained through material properties and finite element modeling studies. Details of the package technology qualification process and results are presented.

Overmold technology applied to cavity down ultrafine pitch PBGA package

The transfer molding technology is normally used for leadframe type packages and chip-up PBGA (Plastic Ball Grid Array) packages. This technology has been applied to cavity down PBGA packages where, normally, a liquid epoxy is dispensed by a needle in the cavity in order to cover the device and gold wires without exceeding the solder ball height plane. The new encapsulation approach using transfer molding process as well as the debug/qualification method and results using an ultrafine pitch wirebond PBGA process are described.

Molding challenges of LOC packages with large devices

This paper presents the manufacturing challenges that were met for plastic encapsulation of lead on chip (LOG) products with large device-to-package area ratios. A new methodology for optimizing product and process performance has been used to eliminate the injection problems which were encountered with these packages. The influence of pellet preheat time and clamping force on the voids and on the knit-lines has been clearly demonstrated in a screening study. The injection speeds have been optimized to completely eliminate the emergence of the defects in a subsequent focusing study.

Void-Free Underfill Process With Variable Frequency Microwave for Higher Throughput in Large Flip Chip Package Application

Moisture voiding in underfill materials can cause reliability issues for the flip chip packages. The bake-out step included in the assembly process flow to avoid this problem cannot be completely efficient for some large die size packages. This is due to complex substrate circuit designs and time delays subsequent to the bake-out step. This paper proposes using the variable frequency microwave cure to eliminate the moisture voiding of flip chip large packages assembled without any bake-out step. Results showed, for a given ramp rate, a decrease in voiding formation with decreasing VFM cure temperature. It was also found that, at low final cure temperatures, the hold steps promoted the voids formation more than the ramp steps. At high final cure temperatures, both ramp and hold steps induced voids formation, growth, and coalescence. Another interesting observation was that a slower ramp rate reduced void formation even at high cure temperature. Based on the voiding evolution study done here, two optimized cure profiles were proposed, one comprising a two-step approach and another using a one-step cure with a low ramp rate of 2 °C/min. These optimized VFM profiles demonstrated good adhesion and reliability results while providing a void-free underfill process without the need for a time-consuming bake-out step.

Study of Capillary Underfill Filler Separation in Advanced Flip Chip Packages

The key role that underfill materials play in highly reliable, advanced flip chip organic packages has generated an increased focus on their behavior and structure. One such behavior relates to the observation of filler separation from the resin matrix which, to date, has been predominantly attributed to gravity or capillary flow. The phenomenon of silica filler separation is discussed in the context of fine pitch, lead-free solder joints with copper-base (pedestal or pillar) under bump metallization and large die packages. The principle mechanism driving filler separation in these structures was confirmed as a migration of the electrostatically charged filler particles away from the copper regions and towards the solder regions of the interconnect. Based on this finding, various factors that influence the surface of the interconnects or the nature and the mobility of the filler particles during the bond and assembly process were explored. It was found that the oxide states and contact angles of the interconnect surfaces do not appear to impact the degree of filler separation. Within the range explored, average filler particle size is ineffective in changing the separation behavior. On the other hand, lower filler content somewhat increases the extent of separation and is believed to be related to an increase in particle mobility. Assembly process variables with known effects on surface interactions and underfill flow were also studied, revealing no observable shift in the occurrence of filler separation. Finally, and most importantly, a reliability study was conducted to investigate the impact of this phenomenon in a very large die (23 × 23 mm2) flip chip organic package subjected to a high level of thermomechanical stress. Using extended Deep Thermal Cycling to 2000 cycles (as opposed to the standard 1000 cycle criterion), no packaging failures occurred and no signs of interconnect degradation were observed. These results are consistent with finite element modeling of the tested package, which showed that stress changes from filler separation in regions of similar dimensions to those that were experimentally observed were within the limits of model error and typical manufacturing variability.

Effect of Underfill Formulation on Large-Die, Flip-Chip Organic Package Reliability: A Systematic Study on Compositional and Assembly Process Variations

Selection of appropriate underfills (or encapsulants) for flip-chip packages is critical to their reliability. In this research article, we present a comprehensive study geared towards the development of such materials. Several underfill formulations were developed based on the target material property guidelines obtained from parametric numerical simulations. Material parameters such as base resin composition, filler particle size, filler particle surface treatment and adhesive strength were modulated to arrive at an optimal composite material composition which facilitated package assembly. The robustness of these formulations was further evaluated by conducting post-assembly thermal cycling tests. Results on the reliability performance of these tailor-made underfills along with the failure analysis studies and correlation with numerical modeling will be presented.

Improvements and alternatives for ultra fine pitch encapsulation

Wire bond plastic ball grid array encapsulation processes, namely the glob top and the transfer molding, have rapidly evolved over the last few years in ultra fine pitch packaging. This paper presents the different alternatives that were studied for both processes in order to overcome the technical challenges of the new high density type packages. A comparative study of the different available glob top valves and pumps is presented as well as new transfer molding process improvements. It is shown that even if today both encapsulation processes have their own individual advantages and product niches, there is a need and a newly developed solution to merge them for future technology applications.