Mark P. Baze

Comparison of error rates in combinational and sequential logic

A pulsed laser was used to demonstrate that, for transients much shorter than the clock period, error rates in sequential logic were independent of frequency, whereas error rates in combinational logic were linearly dependent on frequency. In addition, by measuring the error rate as a function of laser pulse energy for fixed clock frequency, the logarithmic dependence of the SEU vulnerable time period prior to the clock edge in combinational logic was established. A mixed mode circuit simulator program was used to successfully model the dynamic response of the logic circuit to pulses of laser light.

A digital CMOS design technique for SEU hardening

A new cell design technique is described which may be used to create SEU hardened circuits. The technique uses actively biased, isolated well transistors to prevent transients in combinational logic from reaching the output node.

HBD layout isolation techniques for multiple node charge collection mitigation

A three-dimensional (3D) technology computer-aided design (TCAD) model was used to simulate charge collection at multiple nodes. Guard contacts are shown to mitigate the charge collection and to more quickly restore the well potential, especially in PMOS devices. Mitigation of the shared charge collection in NMOS devices is accomplished through isolation of the P-wells using a triple-well option. These techniques have been partially validated through heavy-ion testing of three versions of flip-flop shift register chains.

Single Event Upsets in Deep-Submicrometer Technologies Due to Charge Sharing

Circuit and 3D technology computer aided design mixed-mode simulations show that the single event upset vulnerability of 130- and 90-nm hardened latches to low linear energy transfer (LET) particles is due to charge sharing between multiple nodes as a result of a single ion strike. The low LET vulnerability of the hardened latches is verified experimentally.

Directional Sensitivity of Single Event Upsets in 90 nm CMOS Due to Charge Sharing

Heavy-ion testing of a radiation-hardened-by-design (RHBD) 90 nm dual interlocked cell (DICE latch) shows significant directional sensitivity results impacting observed cross-section and LET thresholds. 3-D TCAD simulations show this directional effect is due to charge sharing and parasitic bipolar effects due to n-well potential collapse.

Propagating SET Characterization Technique for Digital CMOS Libraries

A circuit architecture based on simple logic gates is described which uses small chip areas and low speed testing to characterize single event transients for digital applications. Utility of this architecture is demonstrated with heavy ion data on a 130 nm library

Enhanced TID Susceptibility in Sub-100 nm Bulk CMOS I/O Transistors and Circuits

This paper evaluates the radiation responses of 2.5 V I/O transistors and regular-threshold MOSFETs from a 90 nm commercial bulk CMOS technology. The data obtained from Co ionizing radiation experiments indicate enhanced TID susceptibility in I/O devices and circuits, which is attributed to the p-type body doping. A quantitative model is used to analyze the effects of doping and oxide trapped charge buildup along the sidewall of the shallow trench isolation oxide. These effects are captured in the general electrostatic equation for surface potential, which can be correlated to off-state leakage current. Device simulations are used in concert with experimental measurements and the analytical model to provide physical insight into the radiation response of each device type.

Mitigation Techniques for Single-Event-Induced Charge Sharing in a 90-nm Bulk CMOS Process

In this paper, mitigation techniques to reduce the increased SEU cross section associated with charge sharing in a 90-nm dual-interlocked-cell latch are proposed. The increased error cross section is caused by heavy-ion angular strikes depending on the direction of the ion strike, thereby exacerbating charge sharing among multiple circuit nodes. The use of nodal spacing as a mitigation technique shows an order of magnitude decrease on upset cross section as compared to a conventional layout, and the use of guard-rings show no noticeable effect on upset cross section.

Single Event Upsets in a 130 nm Hardened Latch Design Due to Charge Sharing

Critical charge to represent a logic HIGH is steadily decreasing with decreasing technology feature size. Many methods have been developed to increase critical charge requirement for storage elements, thereby reducing the soft error rates. Design-based approaches have been proposed that use four storage nodes instead of two nodes to retain data. Such designs are considered single event upset (SEU) immune at low energy ion hits for all practical purposes because a single ion hit at a storage node does not cause an upset. However, such designs are vulnerable to ion hits that result in multiple nodes collecting charges. For deep sub-micron technologies, the proximity of circuit nodes results in charge collection at multiple nodes when a single ion strikes a node. Researchers first observed the effect of such charge sharing in SRAM designs. In this paper, circuit and 3D technology computer aided design (TCAD) mixed-mode simulations are used to characterize charge sharing between sensitive pairs of devices and the resulting upsets in a hardened storage cell. The simulation results were verified with experimental data showing upsets due to charge sharing in a hardened cell when exposed to low energy ions

Integrating Circuit Level Simulation and Monte-Carlo Radiation Transport Code for Single Event Upset Analysis in SEU Hardened Circuitry

Monte-Carlo radiation transport code is coupled with SPICE circuit level simulation to identify regions of single event upset vulnerability in an SEU hardened flip-flop, as well as predict single event upset cross sections and on-orbit soft error rates under static and dynamic operating conditions.