Karen Geens

CMOS Process-Compatible High-Power Low-Leakage AlGaN/GaN MISHEMT on Silicon

We report on a novel Au-free CMOS process-compatible process for AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors. The process starts from a 150-mm GaN-on-Si substrate with an embedded Si₃N₄/Al₂O₃ bilayer gate dielectric, encapsulated by a high-temperature low-pressure chemical vapor deposited nitride layer. Power devices with a 20-mm gate width reach a maximum output current of 8 A, a breakdown voltage of 750 V, and a specific on-resistance <i>R</i>_{on, sp} of 2.9 mΩ·cm². The off-state drain leakage at 600 V is 7 μA. We show robust gate dielectrics with a large gate bias swing.

AlGaN/GaN/AlGaN Double Heterostructures Grown on 200 mm Silicon (111) Substrates with High Electron Mobility

In this work, we demonstrate, for the first time, Al0.35GaN/GaN/Al0.25GaN double heterostructure field effect transistors on 200 mm Si(111) substrates. Thick crack-free Al0.25GaN buffer layers are achieved by optimizing Al0.75GaN/Al0.5GaN intermediate layers and AlN nucleation layers. The highest buffer breakdown voltage reaches 1380 V on a sample with a total buffer thickness of 4.6 µm. According to Van der Pauw Hall measurements, the electron mobility is 1766 cm2 V-1 s-1 and the electron density is 1.16×1013 cm-2, which results in a very low sheet resistance of 306±8 Ω/square.

Record Breakdown Voltage (2200 V) of GaN DHFETs on Si With 2-

In this letter, we present a local substrate removal technology (under the source-to-drain region), reminiscent of through-silicon vias and report on the highest ever achieved breakdown voltage (V_BD) of AlGaN/GaN/AlGaN double heterostructure FETs on a Si (111) substrate with only 2-μm-thick AlGaN buffer. Before local Si removal, V_BD saturates at ~700 V at a gate-drain distance (L_GD) ≥ 8 μm. However, after etching away the substrate locally, we measure a record V_BD of 2200 V for the devices with L_GD = 20 μm. Moreover, from Hall measurements, we conclude that the local substrate removal integration approach has no impact on the 2-D electron gas channel properties.

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In this letter, we present a novel approach to enhance the breakdown voltage (<i>V</i>_BD) for AlGaN/GaN/AlGaN double-heterostructure FETs (DHFETs), grown by metal-organic chemical vapor deposition on Si (111) substrates through a silicon-substrate-removal and a layer-transfer process. Before removing the Si substrate, both buffer isolation test structures and DHFET devices showed a saturation of <i>V</i>_BD due to the electrical breakdown through the Si substrate. We observed a <i>V</i>_BD saturation of 500 V for isolation gaps larger than 6 μm . After Si removal, we measured a <i>V</i>_BD enhancement of the AlGaN buffer to 1100 V for buffer isolation structures with an isolation gap of 12 μm. The DHFET devices with a gate-drain (<i>L</i>_GD) distance of 15 μm have a V_BD > 1100 V compared with ~300 V for devices with Si substrate. Moreover, from Hall measurements, we conclude that the substrate-removal and layer-transfer processes have no impact on the 2-D electron gas channel properties.

Buffer Thickness by Local Substrate Removal

Au-free CMOS-compatible AlGaN/GaN HEMT devices have been processed on 200 mm Si substrates u sing a typical CMOS tool set. This paper addresses the challenges with respect to the AlGaN/GaN epitaxy, the processing of thick and bowed 200 mm GaN-on-Si wafers, the impact of Ga contamination on the tools, etc.. An enhancement mode AlGaN/GaN MISHEMT process based on barrier recess is used as demonstrator, and yielded fully functional power devices.

Silicon Substrate Removal of GaN DHFETs for Enhanced (<1100 V) Breakdown Voltage

Au-free GaN-based metal-insulator-semiconductor high electron-mobility transistors grown on 150-mm Si substrates are reported. The device characteristics for three different processes are compared: an ohmic-first and a gate-first process with Al₂O₃-only as gate dielectric and a novel approach with a bilayer gate dielectric stack consisting of Si₃N₄ and Al₂O₃. The Si₃N₄ layer was deposited in situ in the metal-organic chemical vapor deposition reactor in the same growth sequence as the rest of the epilayer stack and the Al₂O₃ layer was deposited ex situ by atomic layer deposition. Only the process with the bilayer gate dielectric results in robust devices with a breakdown voltage >600 V. The ohmic contact resistance for Au-free Ti/Al/W metallization scheme is <;1 Ω·mm. The devices show high maximum output current density (>0.4 A/mm); and low gate and drain leakage (<;10^-10 A/mm). The maximum pulsed mode drain-source current of power bars with 20 mm gate width is 8 A. The specific on-state resistance is 2.9 m Ω·cm².

Au-free CMOS-compatible AlGaN/GaN HEMT processing on 200 mm Si substrates

It is commonly accepted that interface states at the passivation surface of AlGaN/GaN heterostructures play an important role in the formation of the 2DEG density. Several interface state models are cited throughout literature, some with discrete levels, others with different kinds of distributions, or a combination of both. The purpose of this article is to compare the existing interface state models with both direct and indirect measurements of these interface states from literature (e.g., through the hysteresis of transfer characteristics of Metal-Insulator-Semiconductor High Electron Mobility Transistors (MISHEMTs) employing such an interface in the gate region) and Technology Computer Aided Design (TCAD) simulations of 2DEG densities as a function of the AlGaN thickness. The discrepancies between those measurements and TCAD simulations (also those commonly found in literature) are discussed. Then, an alternative model inspired by the Disorder Induced Gap State model for compound semiconductors is proposed. It is shown that defining a deep border trap inside the insulator can solve these discrepancies and that this alternative model can explain the origin of the two dimensional electron gas in combination with a high-quality interface that, by definition, has a low interface state density.

Fabrication and Performance of Au-Free AlGaN/GaN-on-Silicon Power Devices With

We describe the fabrication and characteristics of high voltage enhancement mode SiN/AlGaN/GaN/AlGaN double heterostructure FET devices. The Si3N4 not only acts as a passivation layer but is crucial in the device concept as it acts as an electron donating layer (1). By selective removal under the gate of the in-situ SiN, we realize e-mode operation with a very narrow threshold voltage distribution with an average value of +475 mV and a standard deviation of only 15 mV. Compared to the reference depletion mode devices, we see no impact of the e-mode architecture on the breakdown behaviour. The devices maintain very low leakage currents even at drain biases up to 80% of the breakdown voltage.

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We report on the first measurement results to obtain over 2 kV breakdown voltage (VBD) of GaN-DHFETs on Si substrates by etching a Si Trench Around Drain contacts (STAD). Similar devices without trenches show VBD of only 650 V. DHFETs fabricated with STAD technology show excellent thermal performance confirmed by electrical measurements and finite element thermal simulations. We observe lower buffer leakage at high temperature (100°C) after STAD compared to devices with Si substrate, enabling high temperature device operation.

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Monolithic integration of a half bridge on the same GaN-on-Si wafer is very challenging because the devices share a common conductive Si substrate. In this letter, we propose to use GaN-on-SOI (silicon-on-insulator) to isolate the devices by trench etching through the GaN/Si(111) layers and stopping in the SiO2 buried layer. By well-controlled epitaxy and device fabrication, high-performance 200 V enhancement-mode (e-mode) p-GaN high electron mobility transistors with a gate width of 36 mm are achieved. This letter demonstrates that by using GaN-on-SOI in combination with trench isolation, it is very promising to monolithically integrate GaN power systems on the same wafer to reduce the parasitic inductance and die size.