Martin Mazur

A novel approach for the patterning and high-volume production of sub-40-nm gates

A novel approach for the patterning and manufacturing of sub-40-nm gate structures is presented. Rather than using resist or an inorganic hardmask as the patterning layer, this gate patterning scheme uses an amorphous carbon (a:C) and cap hardmask to pattern small gates. Healthy and manufacturable gate lengths have been achieved below 35 nm with this scheme, and the potential exists for further extendibility.

ACLV-analysis in production and its impact on product performance

The paramount importance of CD-control for logic speed is well recognized. Whereas across wafer-line-width-variation (AWLV) influences the width of the speed distribution, across chip line-width-variation (ACLV) is a dominating factor for device leakage. In our study we will discuss different ACLV-terms based on AMD’s 0.18 and 0.13μm processes. We will show how the variation of different scanner and reticle-parameters affects both random and systematic ACLV-components. We will show that the systematic part either can be dominated by global or layout-specific CD-signature, depending on the reticle manufacturing process, scanner condition and the circuit design. In particular we will discuss the impact of defocus, lens aberrations, illumination uniformity dose accuracy and flare. Eventually, we will show the response of critical performance parameters of state of the art μPs and we will judge different parameters with respect to their impact on μP-speed. Focus control and flare control are found to be the most critical tasks. We will discuss appropriate methods to ensure both focus and flare don’t affect device performance negatively.