Osamu Arisumi

Ferroelectric Properties of Pb(Zi, Ti)O3 Capacitor with Thin SrRuO3 Films within Both Electrodes.

Ferroelectric properties of a Pb(Zi, Ti)O3 (PZT) capacitor with thin SrRuO3(SRO) films within both electrodes were investigated in detail. Thin SRO films of 10 nm thickness markedly improve the electrical performance, such as switching charge (Qsw), saturation characteristics of the hysteresis curve and imprint performance even at an elevated temperature. It should also be noted that there was no Qsw degradation after 5×1010 read/write cycles at 5 V. No leakage current increase after the test was observed. The results of transmission electron microscope (TEM) and electron dispersive X-ray (EDX) analyses also showed that there is no diffusion of either Sr or Ru in the PZT film. The Qsw increase can be explained by the model in which excess oxygen ions existing in the SRO films drift into the PZT due to the external electric field where they fill the oxygen vacancies in the PZT near the interfaces. We confirmed that the proposed electrode structure was a key to realizing highly reliable ferroelectric random access memories (FRAMs).

Suppression of the floating-body effect in SOI MOSFET's by the bandgap engineering method using a Si/sub 1-x/Ge/sub x/ source structure

The bandgap engineering method using a SiGe source structure is presented as a means to suppress the floating-body effect in SOI MOSFETs. Experiments using Ge implantation are carried out to form a narrow-bandgapped SiGe layer in the source region. It has been confirmed that Ge-implanted SIMOX exhibited a 0.1 eV bandgap narrowing with a relatively low Ge-dosage of 10/sup 16/ cm/sup -2/. The fabricated N-type SOI-MOSFETs exhibited suppressed parasitic bipolar effects, such as improvement of the drain breakdown voltage or latch voltage, and suppression of abnormal subthreshold slope. Advantages over other conventional methods are also discussed, indicating that the bandgap engineering provides a practical method to suppress the floating-body effect.

Suppression of the floating-body effect in partially-depleted SOI MOSFETs with SiGe source structure and its mechanism

SiGe layers were formed in source regions of partially-depleted 0.25-/spl mu/m SOI MOSFETs by Ge implantation, and the floating-body effect was investigated for this SiGe source structure. It is found that the increase of the Ge implantation dosage suppresses kinks in I/sub d/-V/sub d/ characteristics and that the kinks disappear for devices with a Ge dose of 3/spl times/10/sup 16/ cm/sup -2/. The lowering of the drain breakdown voltage and the anomalous decrease of the subthreshold swing are also suppressed with this structure. It is confirmed that this suppression effect originates from the decrease of the current gain for source/channel/drain lateral bipolar transistors (LBJTs) with the SiGe source structure. The temperature dependence of the base current indicates that the decrease of the current gain is ascribed to the bandgap narrowing of the source region.

Novel Pb(Ti, Zr)O3(PZT) Crystallization Technique Using Flash Lamp for Ferroelectric RAM (FeRAM) Embedded LSIs and One Transistor Type FeRAM Devices

A novel method of ferroelectric capacitor formation for Ferroelectrie random access memory (FeRAM) embedded LSIs and one-transistor-type FeRAMs has been developed. Amorphous Pb(Ti, Zr)O3(PZT) films were successfully transformed to the perovskite phase by a flash lamp technique with a crystallization time of 1.2 ms at a substrate temperature of 350°C. A flash lamp energy of 27 J/cm2 was sufficient to form a ferroelectric crystal structure due to rapid thermal effects with little heat diffusion in the depth direction. This technique enabled PZT film crystallization in Pt/PZT/Pt structures on multi-Al wiring layers. Granular PZT grains were observed on Pt, Ru and RuO2 electrodes, which indicates that crystal growth begins from the film surfaces. Ferroelectric property was verified by the process at 350°C maximum temperature. PZT films were also crystallized directly on SiO2. This is useful for the fabrication of embedded FeRAM devices and 1Tr-type FeRAMs. The flash lamp process was found to have great potential for application to dielectric film formation, annealing processes and so on.

Formation of SiGe Source/Drain Using Ge Implantation for Floating-Body Effect Resistant SOI MOSFETs

SiGe was formed by Ge implantation into silicon on insulator (SOI) substrates with the dosage range from 0.5 to 3 x 10 16 cm -2 and subsequent annealing in N 2 . The implantation dosage dependence of the crystalline quality, bandgap and sheet resistance of the SiGe layers are investigated. The implantation damage for Ge dosage up to 1 x 10 16 cm -2 can be removed at a temperature as low as 700°C. A SiGe crystalline network is formed by the annealing at the same time. With a Ge dosage of 1 x 10 16 cm -2 or more, bandgap narrowing of the SiGe layer was detected. Sheet resistances of SiGe N + and P + layers gradually increase for higher Ge dosage. SOI MOSFET characteristics in terms of the floating-body effect with the SiGe source/drain layers are presented. The bandgap narrowing suppresses the floating-body effect of fully depleted SOI MOSFETs, while maintaining the reverse leakage current of the p-n junction between the source/drain and channel at a low level.

Mechanism of the suppression of the floating-body effect for SOI MOSFETs with SiGe source structure

SiGe layers were formed in source regions of partially depleted 0.25 /spl mu/m SOI nMOSFETs with the Ge implantation technique and the floating-body effect was investigated for the SiGe source structure. It was confirmed that kinks in the Id-Vd characteristics and the anomalous lowering of the subthreshold swing were suppressed and that the drain breakdown voltage increased for this structure. The mechanism of this suppression effect is presented for the first time. It is found that this suppression originates from the decrease in the current gain for source/channel/drain lateral bipolar transistors with the SiGe source structure. The temperature dependence of the base current indicates that the bandgap narrowing in the source region is the major reason for the decrease in the current gain.

Lead Content Control in (Pb, La)(Zr, Ti)O3 Films Using Ar/O2 Sequential Rapid Thermal Process

A new method of controlling the lead (Pb) profile in (Pb, La)(Zr, Ti)O3 (PLZT) capacitor films with top and bottom SrRuO3 (SRO) electrodes has been developed using an Ar/O2 sequential crystallization process. This new technique makes it possible to realize good fatigue properties and a low leakage current density in the films. We found that the gas ambient of the rapid thermal process (RTP) affects Pb evaporation behavior during PLZT crystallization; an Ar ambient promotes Pb evaporation more than an O2 ambient. The Ar/O2 sequential RTP was introduced on the basis of the optimum design of the Pb profile in crystallized PLZT films. A good ferroelectric capacitor with a Pt/SRO/PLZT/SRO/Pt structure was achieved by controlling the Pb composition in the bulk of PLZT films as well as at the interfaces to the electrodes, resulting in high endurance and low leakage current density.

Analysis of Si–Ge Source Structure in 0.15 µm SOI MOSFETs Using Two-Dimensional Device Simulation

We describe the technological potential of the bandgap engineering technique involving a Si-Ge source structure in a fully-depleted SOI MOSFET to suppress the floating-body effect. The Si-Ge layer fabricated in the source region acts as an absorber for excess holes in the channel region. The detailed mechanism as well as the structure dependence in SOI MOSFETs with a gate length of 0.15 μm have been studied using a two-dimensional device simulation. It has been found that the improvement in BV ds is strongly dependent on the lateral position of the Si-Ge layer relative to the source-to-channel pn junction. It is further predicted that encroachment of the Si-Ge layer into the channel region achieves the maximum BV ds improvement. The BV ds improvement is predicted to reach 1.5 V if it proves possible to lower the energy barrier at the pn junction in the case where ΔE g = 0.2 eV.

Characteristics of an Oxygen Barrier Based on Bi-layered Ir

For high-density ferroelectric random access memory devices (FeRAMs) with capacitor over plug (COP) structure, oxygen diffusion barriers based on bi-layered Ir have been investigated. This paper describes the detailed characteristics of the barriers. A bi-layered Ir barrier was fabricated by repeating the deposition and RTO treatment of an Ir metal film, which was very effective to obtain excellent barrier properties against oxygen diffusion. Surface roughening was shown after RTO, but can be suppressed by lowering the RTO temperature. The roughening is caused by the formation of a gaseous phase of IrOx during RTO, and not by the formation of Ir hillocks. The stress of the bi-layered Ir barrier is tensile after RTO, which makes further stacking of more layers on the barrier with good adhesion possible. Performance of this barrier was checked using the post annealing in 18O isotope ambient at 650°C for 2 hours. SIMS profile showed the barrier prevented the diffusion of 18O, effectively. The above results strongly suggest that the bi-layered Ir barrier can be applied to the COP structure for high-density FeRAMs.

Oxygen Diffusion Barriers for High-Density FeRAMs

For high-density ferroelectric random access memories (FeRAMs) with capacitor over plug (COP) structure, oxygen diffusion barriers have been investigated. This paper describes the excellent properties of two newly developed diffusion barriers, which are based on a) stoichiometric-IrO 2 films and b) surface treated Ir-films. The IrO 2 barrier was successfully optimized by forming stoichiometric IrO 2 , by deposition temperature control and by decreasing mechanical stress. Surface treatment of Ir-metal layer by using RTO (rapid thermal oxidation) was very effective for obtaining excellent barrier properties, which could be further improved by repeated deposition and RTO treatment leading to bi- or multilayer structures. When applied to fully stacked-PZT capacitors, both barrier types inhibited the oxidation of an underlying W-plug even after annealing at 650C for 2 hours in oxygen ambient. Q sw values of PZT capacitors were around 30 w C/cm 2.