Toshiyuki Ishijima

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

A 64 Mw*1 b/16 Mw*4 b DRAM with 30-ns access time which uses a double-metal layer and 0.4- mu m CMOS technology is reported. The external power supply is 3 V, while memory cell arrays operate at 2.2 V. Key circuits for the 64-Mb DRAM are (1) a latched-sense, shared-sense circuit with open bit-line read-out and folded bit-line rewrite operations (LOF) to reduce inter-bit-line coupling noise, (2) alternatively activated and separately end-located word drivers and X decoders to reduce word-line selection delay, and (3) built-in self test and repair circuits using spare memory cells to reduce test costs and increase chip reliability. >

A capacitor-over-bit-line (COB) cell with a hemispherical-grain storage node for 64 Mb DRAMs

A novel capacitor-over-bit-line (COB) cell with a hemispherical-grain (HSG) poly-Si storage node has been developed. This memory cell provides large storage capacitance by increasing the effective surface area of a simple storage node and is manufacturable by optical delineation. The feasibility of the COB cell for 64-Mb DRAMs has been verified by a 64-kb test memory with 1.8- mu m/sup 2/ cells using a 0.4- mu m design rule, storage capacitance of 30 fF, 7-nm-SiO/sub 2/-equivalent dielectric film, and a storage node height of 0.5 mu m.<<ETX>>

A new DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)

A new dynamic RAM (DRAM) cell structure and its fabrication technology are proposed. The proposed DRAM cell consists of a transistor on a lateral epitaxial silicon layer (TOLE) and a stacked capacitor formed in a trench. It can achieve high immunity to alpha-particle-induced noise and a low parasitic bit-line capacitance. The TOLE structure is produced by a silicon-on-insulator fabrication technology newly developed by combining epitaxial lateral overgrowth and preferential polishing. Reasonable electrical characteristics for the TOLE and high immunity against alpha-particle disturbance for the TOLE cell were confirmed. >

New stacked capacitor structure using hemispherical-grain polycrystalline-silicon electrodes

A new technology which makes storage electrode surfaces uneven has been developed for realizing 64 Mbit dynamic random access memories (DRAMs). This technology utilizes a Si film which is deposited by low‐pressure chemical vapor deposition at 550 °C and has hemispherical grains (HSG). The surface area of the HSG‐Si film is about twice as large as Si films deposited at other temperatures. The specific temperature, 550 °C, corresponds to the transition temperature of the film structure from amorphous to polycrystalline. By applying the HSG‐Si film as the storage electrode of a stacked capacitor, a capacitance of twice the value is obtained. The increase of the capacitance makes it possible to reduce the DRAM cell area, even by using a relatively thick dielectric film, thereby providing higher reliability.

A new soft-error immune DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)

A new DRAM cell structure, based on a new design concept, and a fabrication technology for DRAMs of 16Mbits and beyond are proposed. The proposed cell, called a transistor on a lateral epitaxial (TOLE) silicon layer cell, can achieve high immunity to alpha-particle-induced soft errors and a low parasitic bit line capacitance. The TOLE cell is produced by a silicon-on-insulator (SOI) fabrication technology newly developed by combining epitaxial lateral overgrowth(1)(ELO) and preferential polishing(2)(PP). Reasonable electrical characteristics for the TOLE transistor and excellent immunity against alpha-particle disturbance for the TOLE memory cell are confirmed.

A new VLSI memory cell using capacitance coupling

A new VLSI memory cell, which offers small cell area, about 6F2(where F is the feature size), internal cell gain and high alpha-particle immunity is proposed. Since it employs capacitance coupling in a write operation, it requires only one bit line and is called a Capacitance-Coupling (CC) cell. A CC cell consists of three transistors and a capacitor, which are integrated in a small area by sharing their nodes with one another. The charge is stored in a P+-type diffused layer in a shallow N-type diffused layer. The P+-layer potential controls the readout current which flows through the N-layer. Experimental test devices having a 0.7\microm deep N-layer and 0.2\microm deep P+-layer were fabricated. The complete CC cell operation was confirmed.

Advanced DMOS memory cell using a new isolation structure

Advanced DMOS memory cell structure, which employs a combination of n+buried layer and trench isolation, is proposed. This structure provides a narrower isolation width (∼1.5 µm), about 4 times hold time improvement, higher alpha-particle immunity, and easier p-well design. The alpha-flux acceleration experiment shows that the reflecting potential barrier between n+buried layer and n-substrate reduces the number of diffusing holes from the substrate to about one tenth. A new writing method, which employs capacitance coupling between bit line and charge storage region, is also described. Adopting this writing method, the DMOS cell size can be reduced 20 percent.

A deep-submicron isolation technology with T-shaped oxide (TSO) structure

T-shaped oxide (TSO) isolation has been developed to achieve deep-submicron isolation width for scaled devices. The TSO isolation structure consists of a slit in the silicon substrate filled with an oxide film and a cap oxide film covering it. The slit is narrower than the cap oxide film. Channel-stop boron ions are implanted into the slit sidewall region as well as the cap oxide bottom region through the cap oxide film. For n-channel MOSFETs with TSO isolation, a double hump in the subthreshold curve does not appear and the narrow channel effect is greatly reduced. A 0.3- mu m-wide TSO isolation structure shows excellent electrical characteristics.<<ETX>>

A CMOS/partial-SOI structure for future ULSIs

An MOS transistor formed partly on lateral epitaxial silicon film on insulator (called the TOLE structure) has been proposed and applied to a DRAM cell. The authors have investigated the potential of the CMOS-TOLE structure for application to future ultra-large-scale integrated circuits (ULSIs). The test CMOS-TOLEs had a 400-nm-thick SiO/sub 2/ film for the SOI insulator, a 100 approximately 200-nm-thick silicon film, and a 20-nm-thick gate oxide. The designed channel width and length for the CMOS-TOLEs measured were 20/2 approximately 2.5 and 6/2 mu m. The bulk part length was 1.2 mu m. The advantages and properties of the structure are discussed. It has been estimated that the necessary storage charge for the CMOS-TOLE DRAM is about 40% of that for the bulk CMOS DRAM and that the typical logic gate delay for the CMOS-TOLE is about 60% of that for the bulk CMOS. Parasitic sidewall channel formation, which is a problem for the n-channel TOLE due to its isolation structure, has been suppressed by channel side impurity control. The leakage current level has been reduced to a value approximately ten times larger than that for the conventional bulk junction.<<ETX>>

High Speed 4 kbit Static RAM with Silicide Coated Wiring

A high speed, fully static, and 4096 word by one bit Random Access Memory has been developed, using short channel MOSFETs with platinum silicide (PtSi) coated polysilicon gate and PtSi coated n+ diffusion layer as low resistive wiring. The present RAM was operated on a single 5±1 volt power supply. Its typical performances are 21 nsec address access time, 23 nsec chip select access time, 500 mW operating power and 50 mW stand by power.