K. Terada

A capacitor-over-bit-line (COB) cell with a hemispherical-grain storage node for 64 Mb DRAMs

A novel capacitor-over-bit-line (COB) cell with a hemispherical-grain (HSG) poly-Si storage node has been developed. This memory cell provides large storage capacitance by increasing the effective surface area of a simple storage node and is manufacturable by optical delineation. The feasibility of the COB cell for 64-Mb DRAMs has been verified by a 64-kb test memory with 1.8- mu m/sup 2/ cells using a 0.4- mu m design rule, storage capacitance of 30 fF, 7-nm-SiO/sub 2/-equivalent dielectric film, and a storage node height of 0.5 mu m.<<ETX>>

An effective channel length determination method for LDD MOSFETs

We propose a definition of MOSFET effective channel length (L/sub EFF/), that provides a method of determining L/sub EFF/ as a constant, and external resistance (R/sub EXT/) virtually as a constant, even for lightly doped drain (LDD) transistors. A unified relationship between this L/sub EFF/ and MOSFET drive current (linear and saturation) that is common to a wide range of drain structures was confirmed. Therefore, the L/sub EFF/ is useful, not only for compact analytical models, but also as an index of MOSFET performance applicable to both single drain and LDD devices. The dependence of the channel length on the source/drain structure was clarified by introducing the concept of local contribution to channel length. The L/sub EFF/ varies, even if the metallurgical channel length is fixed, depending on the design of the source/drain.

A new DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)

A new dynamic RAM (DRAM) cell structure and its fabrication technology are proposed. The proposed DRAM cell consists of a transistor on a lateral epitaxial silicon layer (TOLE) and a stacked capacitor formed in a trench. It can achieve high immunity to alpha-particle-induced noise and a low parasitic bit-line capacitance. The TOLE structure is produced by a silicon-on-insulator fabrication technology newly developed by combining epitaxial lateral overgrowth and preferential polishing. Reasonable electrical characteristics for the TOLE and high immunity against alpha-particle disturbance for the TOLE cell were confirmed. >

New stacked capacitor structure using hemispherical-grain polycrystalline-silicon electrodes

A new technology which makes storage electrode surfaces uneven has been developed for realizing 64 Mbit dynamic random access memories (DRAMs). This technology utilizes a Si film which is deposited by low‐pressure chemical vapor deposition at 550 °C and has hemispherical grains (HSG). The surface area of the HSG‐Si film is about twice as large as Si films deposited at other temperatures. The specific temperature, 550 °C, corresponds to the transition temperature of the film structure from amorphous to polycrystalline. By applying the HSG‐Si film as the storage electrode of a stacked capacitor, a capacitance of twice the value is obtained. The increase of the capacitance makes it possible to reduce the DRAM cell area, even by using a relatively thick dielectric film, thereby providing higher reliability.

A new effective channel length determination method for LDD MOSFETs

A novel effective channel length (L/sub eff/) determination method applicable to LDD (lightly doped drain) MOSFETs is described. The new L/sub eff/, which is determined as a constant that minimizes bias-dependent dispersion of external resistance, is suited for representing device performance, both in linear and saturation regions. In addition, the bias-dependent L/sub eff/ previously proposed is discussed and compared with metallurgical channel length. The idea of a local contribution factor to effective channel length is presented for analysis of these methods.<<ETX>>

A new dynamic RAM cell for VLSI memories

A high density dynamic memory cell using DMOS tecnnology (DMOS cell) is proposed. A DMOS cell consists of an n-channel DMOSFET as a read gate and a p-channel MOSFET as a write gate with extensive node sharing, Since the two nDMOSFET threshold states are nondestructively detected, the readout signal voltage is almost invariant to scaling. The cell area, saved by using two polysilicon layers and triple self-aligned structure, is 50-60 % of the conventional one-transistor memory cell area. The DMOS cell was successfully fabricated, and the 1.2 V threshold shift and the 7 µA current difference per 1 µ channel width were obtained for 400 Å gate oxide test cell. The complete memory operation was confirmed with a 2×2 test cell array.

A new soft-error immune DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)

A new DRAM cell structure, based on a new design concept, and a fabrication technology for DRAMs of 16Mbits and beyond are proposed. The proposed cell, called a transistor on a lateral epitaxial (TOLE) silicon layer cell, can achieve high immunity to alpha-particle-induced soft errors and a low parasitic bit line capacitance. The TOLE cell is produced by a silicon-on-insulator (SOI) fabrication technology newly developed by combining epitaxial lateral overgrowth(1)(ELO) and preferential polishing(2)(PP). Reasonable electrical characteristics for the TOLE transistor and excellent immunity against alpha-particle disturbance for the TOLE memory cell are confirmed.

A new VLSI memory cell using capacitance coupling

A new VLSI memory cell, which offers small cell area, about 6F2(where F is the feature size), internal cell gain and high alpha-particle immunity is proposed. Since it employs capacitance coupling in a write operation, it requires only one bit line and is called a Capacitance-Coupling (CC) cell. A CC cell consists of three transistors and a capacitor, which are integrated in a small area by sharing their nodes with one another. The charge is stored in a P+-type diffused layer in a shallow N-type diffused layer. The P+-layer potential controls the readout current which flows through the N-layer. Experimental test devices having a 0.7\microm deep N-layer and 0.2\microm deep P+-layer were fabricated. The complete CC cell operation was confirmed.

A new CMOS structure for low temperature operation with forward substrate bias

A CMOS structure with a local well contact that allows the application of forward substrate bias for both p- and n-well with a single substrate supply is described. Higher driving capability and smaller short channel effects can be realized without device area increase. A propagation delay of 95 ps/stage at V/sub dd/=1.5 V and a temperature of 77 K was obtained with a 0.4- mu m gate length, which is about 1.5 times faster than that of the conventional CMOS structure.<<ETX>>

A new VLSI memory cell using DMOS technology (DMOS cell)

A high-density dynamic memory cell using DMOS technology (DMOS cell) is proposed. A DMOS cell consists of an n-channel DMOSFET as a read gate and a p-channel MOSFET as a write gate with extensive node sharing. Since n-DMOSFET threshold state is nondestructively detected, the readout signal voltage is almost invariant to scaling. The cell area, which is made small by using two polysilicon layers and self-aligned structure, is about 50 percent of the conventional one-transistor memory cell area. An analytic model for DMOS cell readout voltage is proposed. From this model, the optimum DMOS cell structure, which gives more than 0.7-V readout voltage with 2-µm channel length, is found for 5-V power supply operation. Experimental data support this model. A 7-µA readout current per 1-µm channel width is obtained for 400-Å gate oxide test cell. The complete memory operation is confirmed with a 2 × 2 test cell array.