Alan B. Botula

A Thin-Film SOI 180nm CMOS RF Switch Technology

This paper describes a 180nm CMOS thin film SOI technology developed for RF switch applications. For the first time we show that the well-known harmonic generation issue in HRES SOI technologies can be suppressed with one additional mask. Power handling, linearity, and Ron*Coff product are competitive with GaAs pHEMT and silicon-on-sapphire technologies. Index Terms — RF switch, thin film SOI, wireless, CMOS

High performance SOI RF switches for wireless applications

This paper describes 0.18um CMOS silicon-on-insulator (SOI) technology and design techniques for SOI RF switch designs for wireless applications. The measured results of SP4T (single pole four throw) and SP8T (single pole eight throw) switch reference designs are presented. It has been demonstrated that SOI RF switch performance, in terms of power handling, linearity, insertion loss and isolation, is very competitive with those utilizing GaAs pHEMT and silicon-on-sapphire (SOS) technologies, while maintaining a cost and manufacturing advantage.

A Thin-Film SOI 180nm CMOS RF Switch

This paper describes a single pole, single throw (SPST) 180nm CMOS thin film SOI switch developed for the most difficult cellular and 802.11x RF switch applications. We will show that power handling, linearity, insertion loss, isolation and switching times are competitive with switch applications utilizing GaAs pHEMT and silicon- on-sapphire technologies. Index Terms — RF switch, thin film SOI, wireless, CMOS I. INTRODUCTION The majority of transceivers in wireless communication systems require a switch to provide isolation between the transmitter and receiver, and flexibility in connecting the antenna(s) to the transmitter or receiver optimized for the needed communication standard in multi-mode systems. In addition to having sufficient isolation, a switch requires low insertion loss to maintain high transmitter efficiency and low receiver noise figure. High linearity is important to ensure that the amplitude and phase information of the modulated signal is maintained and to prevent intermodulation distortion. Switching times much faster than 1us are important in standards such as 802.11a (1) to ensure the full amount of power is available to or from the antenna when required. These performance requirements have historically motivated the selection of GaAs (2) or silicon-on-sapphire (SOS) technologies (3) for RF switch applications. These technologies provide a semi-insulating or insulating substrate, respectively, that offer small substrate parasitic coupling. Reduced substrate coupling minimizes insertion loss, removes a significant source of harmonic frequency generation, and helps ensure uniform voltage division in the stacked transistor configurations that are required for high power applications. However, integrating multi- mode and multi-band capabilities forces a complex integration of T/R switches, e.g. single-pole nine-throw (SP9T). Such complex switch integration requires high- yielding technology such as silicon based CMOS. GaAs and SOS technologies suffer cost and/or integration disadvantages in comparison with purely silicon technologies. Several authors have investigated RF switches fabricated on silicon wafers using nMOS as the switch device (4-6). Recent technology and design improvements have been closing the gap between silicon switch implementations and GaAs or SOS approaches. This paper describes several SPST switch configurations that have been built using the 180nm silicon-on-insulator (SOI) technology optimized for RF switch applications (7), and their measured results. How these measured results compared to simulations and other technologies are also discussed.

Power handling capability of an SOI RF switch

In this study, we define and investigate the maximum power handling capability (Pmax) in an SOI RF shunt branch switch. One of the critical factor in the Pmax is the non-uniform voltage division across an OFF shunt branch. In this study we provide a simple analytical method to determine the stack voltage imbalance. The Pmax is characterized as a function of various parameters, such as, switch stack height, channel length, Gate and Body bias, and process parameters. Overall, we find that the Pmax can be improved by reducing stack imbalance as well as device leakage currents, namely, GIDL.

Lateral tapered active field-plate LDMOS device for 20V application in thin-film SOI

We present a new device design for 20V application in thin body SOI technology. High breakdown voltage is achieved by forming RX-bound field plates which deplete the drift region of an LDMOS structure using only lateral electric field coupling. A baseline 180nm CMOS SOI process is utilized and RX field plate shapes are designed to result in an essentially uniform longitudinal drift region electric field satisfying the RESURF principal. We studied device scaling and the effect of varying the width and length of the angular RX field plates and their relation to impact ionization rate in both floating body and body-contacted n-channel LDMOS deices. 3D TCAD simulations were used to investigate the effect design parameters on electric field and impact ionization. Unitary 20V rated-LDMOS devices are experimentally demonstrated, verifying a LDMOS option to stacked CMOS for high voltage applications in SOI technology.

Improvements in SOI technology for RF switches

Over the past few years, CMOS Silicon-oninsulator (SOI) has emerged as the dominant technology for RF switches in RF front end modules for cell phones and WiFi. RF SOI technologies were created from silicon processes originally used for high speed logic applications, but the technology was modified to meet the performance needs of RF switches. The RF SOI technologies have been improved to follow the evolving system requirements for insertion loss, isolation, voltage tolerance, linearity, integration and cost. In this paper, the performance results of the latest generations of RF SOI switch technologies from IBM are reviewed and technology elements that contribute to improved performance are discussed. Future improvements are also discussed.

Silicon germanium heterojunction bipolar transistor electrostatic discharge power clamps and the Johnson Limit in RF BICMOS SiGe technology

Achieving radio frequency (RF) performance circuit objectives and electrostatic discharge (ESD) protection will continue to challenge future technology. In this study, we use the ultimate limitation of the transistor (known as the Johnson Limit) as a means to provide an ESD power clamp by utilizing a first low breakdown trigger device and a second high breakdown clamp device. Using the inverse relationship between unity current gain cutoff frequency and breakdown voltage, ESD power clamps are constructed using epitaxial base pseudomorphic silicon germanium (SiGe) heterojunction bipolar transistors in a common-collector Darlington configuration. ESD experimental test results from human body model (HBM), machine model (MM) and transmission line pulse (TLP) testing demonstrate the scaling of ESD power clamps. Design studies of alternative implementations, resistor ballasting and different trigger transistors will be discussed. As a comparative analysis, the SiGe-based ESD power clamps will be compared to CMOS MOSFET-based ESD power clamps. A new dimensionless group is defined to quantify the relationship between the power-to-failure and the maximum power. Additionally, a future SiGe technology is shown to provide insight into the impact of technology scaling on future SiGe ESD power clamps.