Richard A. Phelps

A Thin-Film SOI 180nm CMOS RF Switch Technology

This paper describes a 180nm CMOS thin film SOI technology developed for RF switch applications. For the first time we show that the well-known harmonic generation issue in HRES SOI technologies can be suppressed with one additional mask. Power handling, linearity, and Ron*Coff product are competitive with GaAs pHEMT and silicon-on-sapphire technologies. Index Terms — RF switch, thin film SOI, wireless, CMOS

Improvements in SOI technology for RF switches

Over the past few years, CMOS Silicon-oninsulator (SOI) has emerged as the dominant technology for RF switches in RF front end modules for cell phones and WiFi. RF SOI technologies were created from silicon processes originally used for high speed logic applications, but the technology was modified to meet the performance needs of RF switches. The RF SOI technologies have been improved to follow the evolving system requirements for insertion loss, isolation, voltage tolerance, linearity, integration and cost. In this paper, the performance results of the latest generations of RF SOI switch technologies from IBM are reviewed and technology elements that contribute to improved performance are discussed. Future improvements are also discussed.

A cost-competitive high performance Junction-FET (JFET) in CMOS process for RF & analog applications

in this paper, we present a cost-effective JFET integrated in 0.18µm RFCMOS process. The design is highly compatible with standard CMOS process, therefore can be easily scaled and implemented in advanced technology nodes. The design impact on Ron and Voff is further discussed, providing the insights and guidelines for JFET optimization. Besides the superior flicker noise (1/f noise) characteristics, this JFET device also demonstrates promising RF characteristics such as maximum frequency, linearity, power handling capability, power-added efficiency, indicating a good candidate for RF designs.

Design and optimization of silicon JFET in 180nm RF/BiCMOS technology

In this paper, we discuss a method to extrapolate intrinsic and extrinsic R<inf>on</inf> components for a JFET. The results provide the guideline to lower R<inf>on</inf>, hence to achieve competitive “R<inf>on</inf> vs. pinch off (V<inf>off</inf>)” benchmark. The optimization impacts on channel length scaling and process variation are discussed. Besides, an improved RESURF condition is achieved using one of the experimental conditions. The optimized JFET demonstrates the 50% lowered R<inf>on</inf>, low V<inf>off</inf> of −2.75V, and high BVd<inf>ss</inf> of 11V.