Michael A. Sadd

Silicon nanocrystal non-volatile memory for embedded memory scaling

In this paper, we present key features of silicon nanocrystal memory technology. This technology is an attractive candidate for scaling of embedded non-volatile memory (NVM). By replacing a continuous floating gate by electrically isolated silicon nanocrystals embedded in an oxide, this technology mitigates the vulnerability of charge loss through tunnel oxide defects and hence permits tunnel oxide and operating voltage scaling along with accompanied process simplifications. However, going to discrete nanocrystals brings new physical attributes that include the impact of Coulomb blockade or charge confinement, science of formation of nanocrystals of correct size and density and the role of fluctuations, all of which are addressed in this paper using single memory cell and memory array data.

Hybrid silicon nanocrystal silicon nitride dynamic random access memory

This paper introduces a silicon nanocrystal-silicon nitride hybrid single transistor cell for potential dynamic RAM (DRAM) applications that stores charge in silicon nanocrystals or a silicon nitride charge trapping layer or both. The memory operates in the direct tunneling regime for the tunnel oxide and so presents the possibility of a DRAM with good cycling endurance. The silicon nanocrystals of this hybrid device present intermediate states that facilitate tunneling transport to and from the nitride layer. Short time measurements show that the hybrid silicon nanocrystal silicon nitride based DRAM cell programs and erases much faster than a plain SONOS implementation while offering better data retention, memory signal and longer refresh time than a silicon nanocrystal type DRAM.

A 90nm Embedded 2-Bit Per Cell Nanocrystal Flash EEPROM

A two bit/cell embedded nanocrystal bitcell with low write current SSI program and tunnel erase in which nanocrystals are located under dedicated control gates has been demonstrated. Write bias conditions which mitigate gate disturb in a top erase capable bitcell have been confirmed

Silicon Nanocrystal Nonvolatile Memory

Silicon nanocrystal memory devices [1],[2] such as shown in Fig. 4.1, offer the potential to solve the challenging problem of scaling nonvolatile memories. Scaling of floating-gate (FG) nonvolatile memory cells has been limited to bottom oxide thicknesses in the range of 80–110 A primarily because of the vulnerability to charge loss from the conducting FG through isolated defects in the tunnel oxide that arise after repeated write/erase operations. As a result the FG, operating voltages are in the range of 16–20 V required for erasing the memory cell by Fowler-Nordheim tunneling of carriers from the FG to the channel. This voltage is sometimes split as ±8 to ±10 V using fully isolated wells. Silicon nanocrystal memory cells that store charge in isolated centers inside a gate dielectric are less susceptible to charge loss through isolated defect paths in the tunnel oxide due to their discontinuous nature of charge storage. In other words, an underlying oxide defect leads to charge loss only from charge storage sites in its immediate proximity. Once the impact of defect-mediated charge loss is mitigated, charge loss is primarily due to tunneling and the tunnel oxide in these devices can be scaled down to about 50–60 A based on retention-time requirements. The scaling of the tunnel oxide results in embedded memory modules that can operate with a maximum on-chip voltage of ±6 V, allowing reduction of the memory module size by up to a factor of 2 at the 90-nm technology node, as shown in Fig. 4.2 [3]. Furthermore, this reduction in operating voltage enables sharing of logic I/O device implants with the high-voltage periphery devices, which are used to charge and discharge the memory bitcells in the array. Open image in new window FIGURE 4.1 Silicon nanocrystal nonvolatile memory bitcell showing the floating silicon nanocrystals used for isolated charge storage. A cross-section transmission electron microscopic image through the gate stack of a bitcell and a plan view scanning electron microscopic image of the nanocrystals is also shown. Open image in new window FIGURE 4.2 Memory module size for both conventional FG nonvolatile memory (NVM) and nanocrystal-based NVM showing the approximate factor-of-2 reduction in memory module size for nanocrystal-based NVM.

Gate Disturb Reduction in a Silicon Nanocrystal Flash EEPROM by Means of Natural Threshold Voltage Reduction

Introduction As CMOS technology is scaled to the 90nm node and beyond, silicon nanocrystal nonvolatile memories are receiving increased attention as a replacement for floating gate nonvolatile memories [1, 2]. The thin dielectrics in these memories can lead to excessive gate disturb during the read operation. Of primary concern is the loss of electrons of the program state to the gate through the top oxide overlying the nanocrystals. This loss is the result of tunneling due to the high electric field between the gate and the nanocrystals. It has been shown that reducing the natural threshold voltage (Vt,nat) of the memory cell leads to a reduction in gate disturb [3]. Simple reduction of the Vt,nat by decreasing the substrate doping concentration can result in severely degraded short channel performance, as well as degraded hot carrier injection (HCI) performance during the program operation. Thus, it is desired to construct a substrate doping profile with a light surface concentration to obtain a low Vt,nat, and a heavy doping concentration just below the surface to provide robust short channel performance and good HCI programmability.