Robert F. Steimle

Silicon nanocrystal non-volatile memory for embedded memory scaling

In this paper, we present key features of silicon nanocrystal memory technology. This technology is an attractive candidate for scaling of embedded non-volatile memory (NVM). By replacing a continuous floating gate by electrically isolated silicon nanocrystals embedded in an oxide, this technology mitigates the vulnerability of charge loss through tunnel oxide defects and hence permits tunnel oxide and operating voltage scaling along with accompanied process simplifications. However, going to discrete nanocrystals brings new physical attributes that include the impact of Coulomb blockade or charge confinement, science of formation of nanocrystals of correct size and density and the role of fluctuations, all of which are addressed in this paper using single memory cell and memory array data.

Hybrid silicon nanocrystal silicon nitride dynamic random access memory

This paper introduces a silicon nanocrystal-silicon nitride hybrid single transistor cell for potential dynamic RAM (DRAM) applications that stores charge in silicon nanocrystals or a silicon nitride charge trapping layer or both. The memory operates in the direct tunneling regime for the tunnel oxide and so presents the possibility of a DRAM with good cycling endurance. The silicon nanocrystals of this hybrid device present intermediate states that facilitate tunneling transport to and from the nitride layer. Short time measurements show that the hybrid silicon nanocrystal silicon nitride based DRAM cell programs and erases much faster than a plain SONOS implementation while offering better data retention, memory signal and longer refresh time than a silicon nanocrystal type DRAM.

A 90nm Embedded 2-Bit Per Cell Nanocrystal Flash EEPROM

A two bit/cell embedded nanocrystal bitcell with low write current SSI program and tunnel erase in which nanocrystals are located under dedicated control gates has been demonstrated. Write bias conditions which mitigate gate disturb in a top erase capable bitcell have been confirmed

Gate Disturb Reduction in a Silicon Nanocrystal Flash EEPROM by Means of Natural Threshold Voltage Reduction

Introduction As CMOS technology is scaled to the 90nm node and beyond, silicon nanocrystal nonvolatile memories are receiving increased attention as a replacement for floating gate nonvolatile memories [1, 2]. The thin dielectrics in these memories can lead to excessive gate disturb during the read operation. Of primary concern is the loss of electrons of the program state to the gate through the top oxide overlying the nanocrystals. This loss is the result of tunneling due to the high electric field between the gate and the nanocrystals. It has been shown that reducing the natural threshold voltage (Vt,nat) of the memory cell leads to a reduction in gate disturb [3]. Simple reduction of the Vt,nat by decreasing the substrate doping concentration can result in severely degraded short channel performance, as well as degraded hot carrier injection (HCI) performance during the program operation. Thus, it is desired to construct a substrate doping profile with a light surface concentration to obtain a low Vt,nat, and a heavy doping concentration just below the surface to provide robust short channel performance and good HCI programmability.

A static capacitance probe structure for resolving the sidewall skew angle of Silicon Deep Reactive-Ion Etching

This work presents a static capacitive probe structure that enables quantitative characterization of the effective sidewall skew angle of the Silicon Deep-Reactive-Ion-Etching (DRIE) using static LCR prober at ambient environment. The design is capable of resolving sidewall skew angles around both in-plane axes independently and simultaneously with the same sensitivity. The measured distributions of the sidewall skew angle across 8-inch wafers conform to empirical expectation and correlate tightly with quadrature error distributions measured gyroscopes from the same wafers. This work provides an easy, accurate and batch solution to the long existing challenge of resolving such process features in an industrial manufacturing environment.

Optimization of 90nm Split Gate Nanocrystal Non-Volatile Memory

A 90 nm split gate nanocrystal bitcell has been demonstrated with scaled select gate oxide and adjustable control gate threshold voltage that allows for fast, low power SSI operation and top erase. This bitcell performance is excellent and holds promise for embedded flash applications.